TW201327680A - 半導體裝置之製造方法及基板處理系統 - Google Patents

半導體裝置之製造方法及基板處理系統 Download PDF

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TW201327680A
TW201327680A TW101132433A TW101132433A TW201327680A TW 201327680 A TW201327680 A TW 201327680A TW 101132433 A TW101132433 A TW 101132433A TW 101132433 A TW101132433 A TW 101132433A TW 201327680 A TW201327680 A TW 201327680A
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Taiwan
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film
insulating film
high dielectric
dielectric constant
constant insulating
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TW101132433A
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TWI500084B (zh
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Koji Akiyama
Hirokazu Higashijima
Chihiro Tamura
Shintaro Aoyama
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Tokyo Electron Ltd
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    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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Abstract

本發明提供一種半導體裝置之製造方法，其包含以下工序：第1成膜工序，係於被處理體上成膜第1高介電率絕緣膜；結晶化熱處理工序，係在650℃以上且未達60秒之間熱處理該第1高介電率絕緣膜；以及第2成膜工序，係於該第1高介電率絕緣膜上成膜第2高介電率絕緣膜，該第2高介電率絕緣膜係具有離子半徑小於該第1高介電率絕緣膜之金屬元素的離子半徑之金屬元素，且比介電率係大於該第1高介電率絕緣膜。

Description

半導體裝置之製造方法及基板處理系統
本發明關於一種半導體裝置之製造方法及基板處理系統。
近年來，伴隨著MOSFET(Metal Oxide Semiconductor Field Effect Transistor)之高集積化及高性能化的要求，而使用高介電率膜(High-K膜)來作為閘極絕緣膜。當中，又以鉿氧化物系材料受到矚目，已嘗試著提高氧化鉿(HfO2)等材料的介電率，來降低等價氧化膜厚(Equivalent Oxide Thickness；EOT)。
作為提升HfO2的介電率之方法，例如，已被提出有一種將二氧化鈦(TiO2)等之極化率(polarizability)大的材料添加在HfO2中之方法，或是在高溫下熱處理HfO2膜之方法(例如專利文獻1)等。
專利文獻1：美國專利公開2005/0136690A1號公報
然而，前者的方法由於TiO2等之材料的能帶間隙狹窄，因此所合成之HfO2基底的絕緣膜的能帶間隙亦變得狹窄，而有溢漏電流增加之問題。又，專利文獻1等之後者的方法亦有高介電率材料因高溫熱處理而結晶化，透過所產生之結晶粒界(grain boundary)的電氣傳導，而導致溢漏電流增加之問題。
本發明有鑑於上述情事，其目的在於提供一種能夠同時降低EOT及溢漏電流之半導體裝置的製造方法及基板處理系統。
依據本發明實施型態之範例，係提供一種半導體裝置之製造方法，其包含以下工序：第1成膜工序，係於被處理體上成膜第1高介電率絕緣膜；結晶化熱處理工序，係在650℃以上且未達60秒之間熱處理該第1高介電率絕緣膜；以及第2成膜工序，係於該第1高介電率絕緣膜上成膜第2高介電率絕緣膜，該第2高介電率絕緣膜係具有離子半徑小於該第1高介電率絕緣膜之金屬元素的離子半徑之金屬元素，且比介電率係大於該第1高介電率絕緣膜。
依據本發明，便可提供一種能夠同時降低EOT及溢漏電流之半導體裝置的製造方法及基板處理系統。
以下，參閱添附圖式來加以說明本發明之實施型態。
作為本發明實施型態之半導體裝置的製造方法的一工序，首先，針對處理矽晶圓之方法，參閱圖1加以說明。此處雖係針對處理矽晶圓來形成閘極絕緣膜之範例加以說明，但未限定於此。例如，本發明一實施型態 之半導體裝置的製造方法亦可適用於形成電容器的電容絕緣膜(電容器電容膜)之方法。
圖1係顯示用以說明本發明實施型態之半導體製造裝置的製造方法之流程圖。
首先，以氫氟酸等來洗淨矽晶圓的表面。更進一步地，依需要而進行前處理，其係形成SiO2所構成的界面層(工序100)。SiO2所構成的界面層可藉由以鹽酸-過氧化氫(HCl/H2O2)來洗淨矽晶圓而形成。通常，SiO2所構成的界面層係形成為0.3nm左右。
之後，成膜第1高介電率絕緣膜(工序110)。作為第1高介電率絕緣膜，較佳可使用氧化鉿膜(HfO2)、氧化鋯膜(ZrO2)、氧化鋯鉿膜(HfZrOx)及該等膜的層積膜(例如ZrO2/HfO2層積膜)。本實施型態中，係使用氧化鉿膜，而成膜為2.5nm的膜厚。
第1高介電率絕緣膜的成膜可藉由ALD(原子層沉積：Atomic Layer Deposition)、CVD(化學氣相成長：Chemical vapor deposition)、PVD(物理氣相成長：PhysicalVaporDeposition)等的手法來成膜。當中又以，藉由可在低溫下成膜且段差被覆性良好之ALD來成膜為佳。
藉由CVD或ALD來成膜第1高介電率絕緣膜之情況的原料(前驅物)，在本實施型態中，雖係舉成膜HfO2膜時的前驅物作為一例，但未特別限定於此。作為成膜HfO2膜時的前驅物之其他範例，可使用TDEAH(四(二 乙基胺基)鉿)、TEMAH(四(乙基甲基胺基酸)-鉿)等的胺系有機鉿化合物、HTB(四叔丁醇鉿)等的烷氧化物系有機鉿化合物等。作為氧化劑，可使用O3氣體、O2氣體、H2O氣體、NO2氣體、NO氣體、N2O氣體等。此時，亦可將氧化劑電漿化來提高反應性。
藉由ALD來成膜HfO2膜之情況，係交互地重複使Hf原料薄薄地吸附之程序與供應氧化劑之程序來成膜HfO2膜。又，藉由CVD來成膜HfO2膜之情況，係一邊加熱矽晶圓一邊同時供應Hf原料與氧化劑。此外，藉由ALD來成膜HfO2膜時的成膜溫度通常為150℃~350℃左右，藉由CVD來成膜HfO2膜時的成膜溫度通常為350℃~600℃左右。
成膜第1高介電率絕緣膜後，為了使第1高介電率絕緣膜結晶化，而進行結晶化熱處理(工序120)。
亦可在工序120之前加入電漿處理第1高介電率絕緣膜之工序。圖2係顯示用以說明本發明其他實施型態之半導體裝置的製造方法之流程圖。此實施型態中，除了在工序110與工序120之間加入施予電漿處理之工序(115)以外，其他皆與第1實施型態相同。
藉由電漿處理，可粉碎HfO2的成膜時所殘留之微細構造。因此，工序120之結晶化熱處理時，便會容易析出後述具有高比介電率的Cubic(立方晶)相或Tetragonal(正方晶)相。
成膜為第1高介電率絕緣膜之HfO2膜在低溫下的 主相為穩定相(Monoclinic(單斜晶)相)，故比介電率ε為16左右。另一方面，HfO2膜在高溫下會存在有準穩定相(Cubic相(比介電率ε=29)或Tetragonal相(比介電率ε=70))。因此，藉由以短時間來熱處理(瞬間退火(spike anneal))HfO2膜，便可於HfO2膜析出具有高介電率之Cubic相或Tetragonal相。使其析出Cubic相或Tetragonal相之HfO2膜可藉由急速冷卻，來獲得具有Cubic相或Tetragonal相之HfO2膜。
通常，HfO2膜或TiO2膜會因結晶化而形成結晶粒界，導致擴散係數變大，且容易發生相互擴散。特別是，該等相互擴散在高溫下容易發生，例如，若於形成HfO2膜與TiO2膜後進行結晶化熱處理，則HfO2與TiO2膜便會相互擴散，而有HfO2膜改變成HfTiO膜的情況。此時，HfO膜的能帶偏移會降低至TiO2膜的能帶偏移之值，而導致溢漏電流增加。但是，由於工序120的結晶化熱處理係在成膜第2高介電率絕緣膜(工序130)之前進行，因此，可抑制第1高介電率絕緣膜與第2高介電率絕緣膜之間的相互擴散。
結晶化熱處理，例如，可藉由瞬間退火來進行，其係使用藉由燈具加熱等之RTP(Rapid Thermal Process)裝置。結晶化熱處理的熱處理溫度必須在高介電率絕緣膜的結晶化會發生之溫度(通常為650℃以上)下進行。本實施型態中，係在700℃(減壓N2氛圍下)下進行。又，藉由瞬間退火之熱施加時間較佳為未達60秒，特佳 為0.1秒至10秒。其係因為若藉由瞬間退火之熱施加時間為60秒以上的情況，則HfO2膜的穩定相(Monoclinic相)便會容易析出之緣故。
在結晶化熱處理之工序後，成膜第2高介電率絕緣膜(工序130)。作為第2高介電率絕緣，較佳係使用具有較第1高介電率絕緣膜要高介電率之材料(比介電率大的材料)。又，較佳係使用含有離子半徑較第1高介電率絕緣膜的金屬元素(例如，HfO2的情況為Hf)要小的金屬元素之材料。作為第2高介電率絕緣膜的材料較佳係使用含有離子半徑小的金屬元素之材料的理由如下：其係因為藉由導入含有離子半徑小的金屬元素之材料，則第1高介電率絕緣膜(HfO2)中的空隙便會減少，分子體積會收縮，故電氣特性良好的緣故。
作為第2高介電率絕緣膜的具體範例，可使用二氧化鈦(TiO2)膜、三氧化鎢(WO3膜)及鈦酸鹽膜(例如，以TixMeyOz所表示之鈦酸鹽的膜，作為Me，舉例有Hf、Zr、Ce、Nb、Ta、Si、Al、Sr等)。本發明實施型態中雖係使用TiO2膜、WO3膜，但不限於此。
第2高介電率絕緣膜的成膜可藉由ALD、CVD、PVD等的手法來成膜。成膜第2高介電率絕緣膜之情況，為了抑制第1高介電率絕緣膜與第2高介電率絕緣膜之間的相互擴散，第2高介電率絕緣膜的成膜較佳係儘可能地在低溫下成膜。因此，較佳係使用可在較低溫下成膜之ALD或低溫PVD。
此外，藉由CVD或ALD來成膜第2高介電率絕緣膜之情況，前驅物可由公知者當中來適當地選用。例如，作為Ti的CVD或ALD原料，雖可使用例如TiCl4、Ti(O-iPr)4等，但前驅物不限於該等，而亦可使用其他公知的前驅物。又，作為氧化劑，可使用上述成膜HfO2膜之情況的氧化劑。
第2高介電率絕緣膜的膜厚雖依存於第2高介電率絕緣膜的材質，但較佳為5nm以下。具體來說，使用TiO2來作為第2高介電率絕緣膜之情況，第2高介電率絕緣膜的膜厚較佳為5nm以下。使用WO3之情況，第2高介電率絕緣膜的膜厚較佳為5nm以下，特佳為0.2nm~0.5nm的範圍。若第2高介電率絕緣膜的膜厚超過5nm之情況，則會有因FIBL(Fringing Induced Barrier Lowering)，而導致短通道特性劣化的情況。
在第2高介電率絕緣膜的成膜後，藉由例如PVD來形成TiN等的閘極電極材料，而製造半導體裝置(工序140)。所獲得之半導體裝置通常係在400℃左右的低溫下燒結，來將絕緣膜與矽間的不成對電子電性地非活性化。
[用以實現本發明實施型態之基板處理系統]
接下來，針對用以實施本發明實施型態的半導體製造方法之基板處理系統，參閱圖3加以說明。
圖3係顯示用以實施本發明實施型態的半導體製造方法之基板處理系統的結構例之概略圖。此外，該基 板處理系統200係針對已進行圖1中之工序100的前處理工序後之矽晶圓，進行工序110~工序130的處理，來形成閘極絕緣膜。
如圖3所示，基板處理系統200係具有用以成膜第1高介電率絕緣膜及第2高介電率絕緣膜之2個成膜裝置1、2；以及用以在工序120中結晶化熱處理第1高介電率絕緣膜之結晶化處理裝置4。又，基板處理系統200較佳係具有用以在工序115中電漿處理第1高介電率絕緣膜之電漿處理裝置3。
成膜裝置1、2、結晶化處理裝置4及電漿處理裝置3係分別對應地設置於呈六角形之晶圓搬送室5的4個邊。又，晶圓搬送室5的其他2個邊係分別設置有加載互鎖室6、7。該等加載互鎖室6、7之與晶圓搬送室5呈相反側係設置有晶圓搬出入室8。晶圓搬出入室8之與加載互鎖室6、7呈相反側係設置有安裝有可容納矽晶圓W的3個晶圓匣盒(Foup)F之埠口9、10、11。
成膜裝置1、2、結晶化處理裝置4、電漿處理裝置3及加載互鎖室6、7係透過閘閥G而連接於晶圓搬送室5之六角形的各邊。藉由開放各閘閥G，而與晶圓搬送室5相連通，藉由關閉各閘閥G，而自晶圓搬送室5被阻隔。又，加載互鎖室6、7之連接於晶圓搬出入室8的部分亦設置有閘閥G。加載互鎖室6、7係藉由開放閘閥G而與晶圓搬出入室8相連通，藉由關閉而自晶圓搬出入室8被阻隔。
晶圓搬送室5內係設置有相對於成膜裝置1、2、結晶化處理裝置4、電漿處理裝置3及加載互鎖室6、7進行晶圓W的搬出入之晶圓搬送裝置12。晶圓搬送裝置12係具有配設於晶圓搬送室5的略中央，來將晶圓W保持在可旋轉及伸縮之旋轉．伸縮部13的前端之2個葉片14a、14b。葉片14a、14b係相互朝向相反方向般地安裝在旋轉．伸縮部13。此外，該晶圓搬送室5內係被保持在特定的真空度。
此外，晶圓搬出入室8的頂部係設置有HEPA過濾器(未圖示)。通過HEPA過濾器而被去除有機物或粒子等後的清潔空氣會在下向流(down flow)之狀態下被供應至晶圓搬出入室8內。因此，係在大氣壓的清潔空氣氛圍下進行晶圓W的搬出入。晶圓搬出入室8之晶圓匣盒F安裝用的3個的埠口9、10、11係分別設置有擋門(未圖示)。而構成為將收納有晶圓W或空的晶圓匣盒直接安裝在該等埠口9、10、11，在安裝時，擋門會被卸除來防止外氣侵入同時與晶圓搬出入室8相連通。又，晶圓搬出入室8的側面係設置有對位室15，來進行晶圓W的對位。
晶圓搬出入室8內係設置有進行往晶圓匣盒F之晶圓W的搬出入以及往加載互鎖室6、7之晶圓W的搬出入之晶圓搬送裝置16。晶圓搬送裝置16係具有2個多關節臂，而為可沿著晶圓匣盒F的配列方向在軌道18上行走之構造。晶圓W的搬送係將晶圓W載置於前 端的手部17上來實施。此外，圖3中係顯示其中一手部17存在於晶圓搬出入室8，另一手部則插入至晶圓匣盒F內之狀態。
基板處理系統200的結構部(例如成膜裝置1、2、結晶化處理裝置4、電漿處理裝置3、晶圓搬送裝置12、16)係構成為連接於電腦所構成的控制部20，而受到控制部20的控制。又，控制部20係連接有作業員為了管理系統而進行指令的輸入操作等之鍵盤，或可視化地顯示系統的運轉狀況之顯示器等所構成的使用者介面21。
控制部20另連接有記憶部22，其係儲存有藉由控制部20的控制來實現系統中所執行的各種處理之控制程式，或對應於處理條件來使各構成部執行處理之程式(即處理配方)。處理配方係記憶在記憶部22中的記憶媒體。記憶媒體可為硬碟，或是CDROM、DVD、快閃記憶體等可移動性者。又，亦可為從其他裝置透過例如專用回線來適當地傳送配方之結構。
基板處理系統200中的處理，例如，係藉由以來自使用者介面21的指示等而從記憶部22呼叫出任意的處理配方，並使控制部20執行來實施。此外，控制部20可直接控制各構成部，或是在各構成部設置個別的控制器，而透過該等來控制。
本發明實施型態之基板處理系統200中，首先，係載置收納有已進行前處理後的晶圓W之晶圓匣盒F。接 下來，藉由被保持在大氣壓的清潔空氣氛圍之晶圓搬出入室8內的晶圓搬送裝置16，來將一片晶圓W從晶圓匣盒F取出並搬入至對位室15，以進行晶圓W的對位。接著，將晶圓W搬入至加載互鎖室6、7的任一者，並將加載互鎖室內真空抽氣。藉由晶圓搬送室5內的晶圓搬送裝置12來取出加載互鎖室內的晶圓，並將晶圓W裝入於成膜裝置1，以進行工序110的成膜處理。在第1高介電率絕緣膜的成膜後，藉由晶圓搬送裝置12來將晶圓W取出，較佳地係搬入至工序115的電漿處理裝置3，來進行第1高介電率絕緣膜的電漿處理。之後，藉由晶圓搬送裝置12來取出晶圓W，並插入至結晶化處理裝置4，而施予工序120的結晶化處理。之後，藉由晶圓搬送裝置12來將晶圓W取出，並將晶圓W裝入於成膜裝置2，以進行工序130的成膜處理。在工序130的成膜處理後，藉由晶圓搬送裝置12來將晶圓W搬入至加載互鎖室6、7的任一者，並使加載互鎖室中返回大氣壓。藉由晶圓搬出入室8內的晶圓搬送裝置16來取出加載互鎖室內的晶圓W，並收納在晶圓匣盒F的任一者。針對1批次的晶圓W進行以上般的動作，便結束1套處理。
[成膜裝置1、2的結構例]
接下來，針對用以實施工序110及工序130之成膜裝置1、2的結構，參閱圖4加以說明。圖4係顯示本發明實施型態之成膜裝置1(或2)的結構例之概略圖。此 外，作為藉由成膜裝置1(及2)之第1(及第2)高介電率絕緣膜的較佳成膜方法，雖係針對藉由ALD或CVD來成膜之情況的成膜裝置範例加以說明，但亦可為藉由未圖示之PVD來成膜之結構。
成膜裝置1係具有氣密地構成之略圓筒狀的處理室31，當中係配置有用以水平地支撐被處理體(晶圓W)之晶座32。晶座32的中央下部係設置有圓筒狀的支撐組件33，晶座32係受到支撐組件33的支撐。晶座32係由例如AlN的陶瓷所構成。
又，晶座32係埋入有加熱器35，該加熱器35係連接有加熱器電源36。另一方面，晶座32的上面附近係設置有熱電耦37，熱電耦37的訊號會被傳送至控制器38。然後，控制器38會對應於係熱電耦37的訊號來將指令傳送至加熱器電源36，並控制加熱器35的加熱來將晶圓W控制為特定溫度。
處理室31的內壁、晶座32及支撐組件33的外周係設置有用以防止附著物沉積之石英襯套39。石英襯套39與處理室31的壁部之間流有吹淨氣體(遮護氣體)，藉此防止附著物沉積在壁部，而防止污染。此外，石英襯套39係可拆卸之結構，以便能夠有效率地進行處理室31內的維修保養。
處理室31的頂壁31a係形成有環狀的孔31b，且嵌入有從該處朝處理室31內突出之噴淋頭40。噴淋頭40會將上述成膜用原料氣體噴出至處理室31內，其上部 係連接有導入有原料氣體之第1導入道41，與導入有氧化劑之第2導入道42。
噴淋頭40的內部係上下2層地設置有空間43、44。上側的空間43係連接有第1導入道41，與該空間43相連通之第1氣體噴出路45係延伸至噴淋頭40的底面。下側的空間44係連接有第2導入道42，與該空間44相連通之第2氣體噴出路46係延伸至噴淋頭40的底面。亦即，噴淋頭40係為原料氣體與氧化劑不會混合，而是會均勻地擴散至空間43、44，並分別獨立地從噴出路45及46噴出之後混合型式(post-mixed type)。
此外，晶座32可藉由未圖示之升降機構而升降，並調整製程間隙以使曝露在原料氣體之空間極小化。
處理室31的底壁係設置有朝下方突出之排氣室51。排氣室51的側面係連接有排氣管52，該排氣管52係連接有排氣裝置53。藉由使排氣裝置53作動，便可將處理室31內減壓至特定的真空度。
處理室31的側壁係設置有用以在與晶圓搬送室5之間進行晶圓W的搬出入之搬出入口54，與用以開閉該搬出入口54之閘閥G。
此外，藉由CVD來成膜第1(或第2)高介電率絕緣膜之情況，上述原料氣體會通過第1導入道41，氧化劑會通過第2導入道42而同時被供應至噴淋頭40。藉由ALD來成膜之情況，上述原料氣體及氧化劑係交互地被供應。原料氣體係從例如原料容器壓送液體狀的原 料，並以氣化器來將其氣化而供應。
上述方式構成的成膜裝置中，首先，係在將晶圓W搬入至處理室31內後，將其當中排氣而成為特定的真空狀態，並藉由加熱器35來將晶圓W加熱至特定溫度。此狀態下，CVD的情況係經由第1導入道41及第2導入道42且同時透過噴淋頭40來將原料氣體與氧化劑導入至處理室31內。ALD的情況，則係交互地將該等導入至至處理室31內。
藉此，原料氣體與氧化劑便會在已加熱後的晶圓W上反應，而在晶圓W上成膜有特定的高介電率絕緣膜。
[電漿處理裝置3的結構例]
接下來，針對用以實施工序115之電漿處理裝置3，參閱圖5加以說明。圖5係顯示本發明實施型態之電漿處理裝置3的結構例之概略圖。
此外，此處雖係顯示微波電漿裝置的範例，且為RLSA(Radial Line Slot Antenna)微波電漿方式之微波電漿處理裝置的範例，但未限定於此。
電漿處理裝置3係具有略圓筒狀的處理室81、設置於其當中的晶座82、以及設置於處理室81的側壁且用以導入處理氣體之氣體導入部83。又，電漿處理裝置3係設置為面臨處理室81上部的開口部，且係設置有形成有多個微波穿透孔84a之平面天線84、用以產生微波之微波產生部85、以及將微波引導至平面天線84 之微波傳送機構86。
平面天線84的下方係設置有介電體所構成的微波穿透板91，平面天線84上係設置有密封組件92。密封組件92為水冷構造(未圖示)。此外，平面天線84的上面係設置有介電體所構成的慢波材。
微波傳送機構86係具有從微波產生部85引導微波且延伸於水平方向之導波管101、從平面天線84朝上方延伸之內導體103及外導體104所構成的同軸導波管102、以及設置在導波管101與同軸導波管102之間的模式轉換機構105。處理室81的底壁係設置有排氣管93，透過該排氣管93且藉由未圖示之排氣裝置，便可將處理室81內減壓至特定的真空度。
又，晶座82亦可連接有離子吸引用之高頻電源106。晶座82係埋入有加熱器87，該加熱器87係連接有加熱器電源88，藉由來自加熱器電源88的電壓，來控制加熱器87的加熱，而將晶圓W控制為特定溫度。
電漿處理裝置3會將微波產生部85所產生的微波透過微波傳送機構86且以特定模式引導至平面天線84，並通過平面天線84的微波穿透孔84a及微波穿透板91來均勻地供應至處理室81內。藉由所供應之微波，則從氣體導入部83被供應的處理氣體便會電離或解離而生成電漿，且藉由電漿中的活性種(例如自由基)，來對晶圓W上的第1高介電率絕緣膜進行電漿處理。此外，作為處理氣體，可使用O2氣體、O2氣體及稀有氣 體(非活性氣體)、稀有氣體、稀有氣體及N2氣體。
[結晶化處理裝置4的結構例]
接下來，針對用以實施工序120之結晶化處理裝置4，參閱圖6加以說明。圖6係顯示本發明實施型態之結晶化處理裝置4的結構例之概略圖。
圖6所示之結晶化處理裝置4係構成為使用燈具加熱之RTP裝置，其會對第1高介電率絕緣膜施予瞬間退火。結晶化處理裝置4係具有氣密地構成之略圓筒狀的處理室121，處理室121內係設置有可旋轉地支撐晶圓W之支撐組件122。支撐組件122的旋轉軸123係朝下方延伸，且會藉由處理室121外的旋轉驅動機構124而旋轉。藉此，則晶圓W便會連同支撐組件122一起旋轉。
處理室121的外周係環狀地設置有排氣路徑125，處理室121與排氣路徑125係透過排氣孔126而相連接。然後，排氣徑路125的至少1個部位處係連接有真空幫浦等之排氣機構(未圖示)，來將處理室121內排氣。
處理室121的頂壁係插入有氣體導入管128，氣體導入管128係連接有氣體供應管129。亦即，透過氣體供應管129及氣體導入管128來將處理氣體導入至處理室121內。作為處理氣體，較佳可使用Ar氣體等之稀有氣體或N2氣體。
處理室121的底部係設置有燈具室130，燈具室130的上面係設置有石英等之透明材料所構成的透光板131 。燈具室內係設置有複數加熱燈132，便可加熱晶圓W。此外，燈具室130的底面與旋轉驅動機構124之間係圍繞旋轉軸123般地設置有波紋管133。
結晶化處理裝置4中，首先，係在將晶圓W搬入至處理室121內後，將其當中排氣而成為特定的真空狀態。之後，一邊將處理氣體導入至處理室121內，一邊藉由旋轉驅動機構124且透過支撐組件122來旋轉晶圓W，並藉由燈具室130的燈具132來使晶圓W急速升溫，而在成為特定溫度之時間點關閉燈具132來急速地降溫。藉此，便可在短時間內進行結晶化處理。
此外，亦可不一定要旋轉晶圓W。又，亦可為將燈具室130配置在晶圓W的上方之結構。此情況下，亦可於晶圓W的內面側設置有冷卻機構，而可更急速地降溫之結構。
[實施型態]
接下來，針對使用本發明實施型態之半導體的製造方法之效果的實證加以說明。
<<第1實施型態>>
首先，以氫氟酸等來洗淨矽晶圓的表面。藉由以鹽酸-過氧化氫來洗淨洗淨後的矽晶圓，而形成SiO2所構成的界面層(工序100)。針對形成後的矽晶圓W，藉由ALD來成膜作為第1高介電率絕緣膜之2.5nm的HfO2(工序110)，並施予700℃的瞬間退火處理(工序120)。再藉由PVD來成膜作為第2高介電率絕緣膜之3nm的 TiO2(工序130)。之後，藉由PVD來形成作為閘極電極之10nm的TiN(工序140)，並施予10分鐘、400℃的低溫熱處理，藉以製造實施例1的半導體裝置。
又，作為比較例，係顯示未施予工序120的瞬間退火之範例、未成膜工序130的第2高介電率絕緣膜之範例、以及於工序130後施予高溫熱處理之範例。此外，將實施例及比較例的詳細製造條件顯示於圖7(表1)。
表1係顯示實施例及比較例中所獲得之半導體裝置的EOT(nm)及溢漏電流(A/cm2)。又，表1亦顯示有平帶電壓(VFB；V)。
由表1可知實施例1中所獲得之半導體裝置的EOT最小。另一方面，關於溢漏電流，比較例1的方法雖較實施例1的方法溢漏電流較小，但EOT為1nm以上。亦即，可得知實施例的方法能夠降低EOT，同時抑制溢漏電流(可同時達成EOT與溢漏電流的特性值)。
圖8係顯示藉由高分解能拉塞福背向散射分析裝置(HR-RBS)之實施例1(圖8A)及比較例2(圖8B)中所獲得之各元素的濃度分佈相對於半導體裝置的深度方向。此外，橫軸的軸向係使矽晶圓W為下面而靜置在水平的面之情況下，以TiO2膜的上面為0nm，而從TiO2膜的上面朝向鉛直方向下方之方向。
由圖8B可知比較例的方法所獲得之半導體裝置係在第1高介電率絕緣膜(HfO2膜)與第2高介電率絕緣膜(TiO2膜)的界面處，Hf與Ti會相互擴散。特別是，Hf 會擴散至TiO2相的深處，其係成為溢漏電流增加的原因之一。Hf與Ti的相互擴散的增加推測為在HfO2膜及TiO2膜的成膜後，由於係在高溫(700℃)下施予的結晶化熱處理，因此會形成有結晶粒界，導致擴散係數變大的緣故。
另一方面，由圖8A可知實施例的方法所獲得之半導體裝置相較於比較例的方法所獲得之半導體裝置，Hf與Ti的相互擴散係受到抑制。推測其係因為在HfO2膜的成膜後施予結晶化熱處理，之後，成膜TiO2膜，但在TiO2膜的成膜後未在高溫下施予熱處理的緣故。
<<第2實施型態>>
接下來，針對實際證明了本發明實施型態之半導體裝置的製造方法中，瞬間退火(短時間熱處理，工序120)的效果之實驗，參閱圖9加以說明。
圖9係顯示本發明實施型態之半導體裝置的製造方法中，成膜後之膜的X射線繞射(XRD)分析結果。
首先，以氫氟酸等來洗淨矽晶圓的表面。藉由以鹽酸-過氧化氫來洗淨洗淨後的矽晶圓，而形成SiO2所構成的界面層(工序100)。針對形成後的矽晶圓W，藉由ALD來成膜作為第1高介電率絕緣膜之2.5nm的HfO2(工序110)，並施予700℃的瞬間退火處理(工序120)。再藉由PVD，來成膜作為第2高介電率絕緣膜之3nm的TiO2(工序130)。有關於上述方式獲得之膜的XRD分析結果，圖9中係以實線來顯示實施例。又，圖9中作 為比較例，係將工序120中，在900℃下進行10分鐘熱處理，但未進行後續的處理之膜的XRD分析結果，以虛線來顯示。
由圖9可知比較例的方法所獲得之膜，因熱處理，而觀察到來自穩定相(Monoclinic相(比介電率ε=16左右))的尖峰。另一方面，實施例的方法所獲得之膜，由於係在HfO2膜的成膜後施予短時間的結晶化熱處理(瞬間退火)，之後，成膜TiO2膜，但TiO2膜的成膜後未在高溫下施予熱處理，因此觀察到來自準穩定相(Cubic相(比介電率ε=29左右))的尖峰。亦即，推測藉由本發明實施型態之半導體裝置的製造方法，由於可有效率地析出比介電率高之HfO2相(例如Cubic相)，因此實施例中所獲得之膜的電氣特性便提高。
<<第3實施型態>>
接下來，針對實際證明了本發明實施型態之半導體裝置的製造方法中，電漿處理工序(工序115)的效果及第2高介電率絕緣膜的膜厚之實驗加以說明。
首先，以氫氟酸等來洗淨矽晶圓的表面。藉由以鹽酸-過氧化氫來洗淨洗淨後的矽晶圓，而形成SiO2所構成的界面層(工序100)。針對形成後的矽晶圓W，藉由ALD來成膜作為第1高介電率絕緣膜之2.5nm的HfO2(工序110)，並對HfO2膜施予電漿處理。此時，一部分的例子中，並未施予電漿處理。之後，施予700℃的瞬間退火處理(工序120)。再藉由PVD來成膜作為第2高 介電率絕緣膜之0~5nm的TiO2(0nm係指未成膜有TiO2的情況)(工序130)。之後，形成作為閘極電極之10nm的TiN(工序140)，並藉由施予10分鐘、400℃的低溫熱處理，來製造半導體裝置。
第3實施型態中，係將實施例及比較例的詳細製造條件顯示於圖10的表2。
表2係顯示實施例及比較例中所獲得之半導體裝置的EOT(nm)及溢漏電流(A/cm2)。又，表2亦顯示有平帶電壓(VFB；V)。
由表2確認了藉由施予電漿處理，可達成EOT的薄膜化及溢漏電流的抑制。推測其係因為藉由電漿處理，則HfO2的成膜時所殘留之微細構造會被粉碎，而在結晶化熱處理時，容易析出具有高比介電率的Cubic相或Tetragonal相之緣故。
又，由表2可知本實施型態的實施範圍中，EOT及溢漏電流皆與第2高介電率絕緣膜的膜厚依存性小，因此藉由成膜(層積)5nm以下的第2高介電率絕緣膜，可達成EOT的薄膜化及溢漏電流的抑制。
<<第4實施型態>>
接下來，針對本發明實施型態之半導體裝置的製造方法中，成膜作為第2高介電率絕緣膜的WO3之情況加以說明。
首先，以氫氟酸等來洗淨矽晶圓的表面。藉由以鹽酸-過氧化氫來洗淨洗淨後的矽晶圓，而形成SiO2所構 成的界面層(工序100)。針對形成後的矽晶圓W，藉由ALD來成膜作為第1高介電率絕緣膜之2.5nm的HfO2(工序110)。之後，施予700℃的瞬間退火處理(工序120)。再藉由PVD來成膜作為第2高介電率絕緣膜之0.2~5nm的WO3(工序130)。之後，形成作為閘極電極之10nm的TiN(工序140)，並藉由施予10分鐘、400℃的低溫熱處理，來製造半導體裝置。
第4實施型態中，係將實施例的詳細製造條件顯示於圖11的表3。表3中作為參考，亦顯示了表1之實施例1及比較例5的條件及結果。
表3係顯示實施例及比較例中所獲得之半導體裝置的EOT(nm)。又，表3亦顯示有平帶電壓(VFB；V)。
由表3可知成膜作為第2高介電率絕緣膜之WO3的情況，藉由成膜0.2nm~0.5nm左右的WO3，可達成EOT的薄膜化。
此外，本發明未限定於上述實施型態，可做各種變化。例如，本發明之閘極絕緣膜的形成方法亦可適用於電容器的電容絕緣膜(電容器電容膜)的形成方法。又，上述實施型態中，雖係使用矽晶圓(矽基板)來作為被處理體，但亦可為其他的半導體基板。
本申請案係依據2011年9月7日所申請之日本專利申請第2011-195246號而主張優先権，並援用其全部內容於本申請案。
1、2‧‧‧成膜裝置
3‧‧‧電漿處理裝置
4‧‧‧結晶化處理裝置
6、7‧‧‧加載互鎖室
20‧‧‧控制部
22‧‧‧記憶部
200‧‧‧基板處理系統
G‧‧‧閘閥
W‧‧‧半導體晶圓
圖1係用以說明本發明一實施型態的範例之半導體製造裝置的製造方法之流程圖。
圖2係用以說明本發明一實施型態的其他範例之半導體製造裝置的製造方法之流程圖。
圖3係顯示用以實施本發明一實施型態的半導體製造方法之基板處理系統的結構例之概略圖。
圖4係顯示本發明一實施型態的實施型態之成膜裝置的結構例之概略圖。
圖5係顯示本發明一實施型態的實施型態之電漿處理裝置的結構例之概略圖。
圖6係顯示本發明一實施型態的實施型態之結晶化處理裝置的結構例之概略圖。
圖7係顯示依據實施例及比較例中所獲得之半導體裝置之EOT、溢漏電流的值，來進行瞬間退火之工序等的效果之表。
圖8A係顯示實施例中所獲得之半導體裝置的深度方向之概略圖。
圖8B係顯示各元素的濃度分佈相對於比較例中所獲得之半導體裝置的深度方向之概略圖。
圖9係顯示本發明一實施型態之半導體裝置的範例之X射線繞射(XRD)分析的結果。
圖10係顯示依據實施例及比較例中所獲得之半導 體裝置之EOT、溢漏電流的值，來進行電漿處理之工序的效果之表。
圖11係顯示依據實施例及比較例中所獲得之半導體裝置之EOT、溢漏電流的值，來成膜作為第2高介電率絕緣膜的WO3之效果之表。
工序100‧‧‧前處理(形成介面SiO2)
工序110‧‧‧成膜第1高介電率絕緣膜(ALD,CVD,PVD)
工序120‧‧‧結晶化熱處理(瞬間退火)
工序130‧‧‧成膜第2高介電率絕緣膜(ALD,CVD,PVD)
工序140‧‧‧形成TiN電極

Claims (10)

  1. 一種半導體裝置的製造方法，其包含以下工序：第1成膜工序，係於被處理體上成膜第1高介電率絕緣膜；結晶化熱處理工序，係在650℃以上且未達60秒之間熱處理該第1高介電率絕緣膜；以及第2成膜工序，係於該第1高介電率絕緣膜上成膜第2高介電率絕緣膜，該第2高介電率絕緣膜係具有離子半徑小於該第1高介電率絕緣膜之金屬元素的離子半徑之金屬元素，且比介電率係大於該第1高介電率絕緣膜。
  2. 如申請專利範圍第1項之半導體裝置的製造方法，其中在該結晶化熱處理工序之前，係包含有電漿處理該第1高介電率絕緣膜之工序。
  3. 如申請專利範圍第1項之半導體裝置的製造方法，其中該結晶化熱處理工序係以瞬間退火(spike anneal)裝置進行。
  4. 如申請專利範圍第1項之半導體裝置的製造方法，其中該第1高介電率絕緣膜為氧化鉿膜、氧化鋯膜、氧化鋯鉿膜或該等膜的層積膜。
  5. 如申請專利範圍第1項之半導體裝置的製造方法，其中該第2高介電率絕緣膜為氧化鈦膜、三氧化鎢膜或鈦酸鹽膜。
  6. 如申請專利範圍第1項之半導體裝置的製造方法 ，其中該第2高介電率絕緣膜的膜厚為5nm以下。
  7. 一種基板處理系統，其具有：第1成膜裝置，係於被處理體上成膜第1高介電率絕緣膜；結晶化熱處理裝置，係在650℃以上且未達60秒之間熱處理該第1高介電率絕緣膜；以及第2成膜裝置，係於藉由該結晶化熱處理裝置之間熱處理後，於該第1高介電率絕緣膜上成膜第2高介電率絕緣膜，該第2高介電率絕緣膜係具有離子半徑小於該第1高介電率絕緣膜之金屬元素的離子半徑之金屬元素，且比介電率係大於該第1高介電率絕緣膜。
  8. 如申請專利範圍第7項之基板處理系統，其另具有控制部，該控制部係控制為會依序進行藉由該第1成膜裝置之成膜處理、藉由該結晶化熱處理裝置之結晶化熱處理、以及藉由該第2成膜裝置之成膜處理。
  9. 一種基板處理系統，其具有：第1成膜裝置，係於被處理體上成膜第1高介電率絕緣膜；電漿處理裝置，係電漿處理該高介電率絕緣膜；結晶化熱處理裝置，係在650℃以上且未達60 秒之間熱處理該第1高介電率絕緣膜；以及第2成膜裝置，係於藉由該結晶化熱處理裝置之間熱處理後，於該第1高介電率絕緣膜上成膜第2高介電率絕緣膜，該第2高介電率絕緣膜係具有離子半徑小於該第1高介電率絕緣膜之金屬元素的離子半徑之金屬元素，且比介電率係大於該第1高介電率絕緣膜。
  10. 如申請專利範圍第9項之基板處理系統，其另具有控制部，該控制部係控制為會依序進行藉由該第1成膜裝置之成膜處理、藉由該電漿處理裝置之電漿處理、藉由該結晶化熱處理裝之結晶化熱處理、以及藉由該第2成膜裝置之第2成膜處理。
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