KR970707582A - 기판의 지형을 수정함으로써 기판상에 평면에 형성하는 방법(forming a planar surface over a substrate by modifying the topography of the substrate) - Google Patents

기판의 지형을 수정함으로써 기판상에 평면에 형성하는 방법(forming a planar surface over a substrate by modifying the topography of the substrate)

Info

Publication number
KR970707582A
KR970707582A KR1019970703143A KR19970703143A KR970707582A KR 970707582 A KR970707582 A KR 970707582A KR 1019970703143 A KR1019970703143 A KR 1019970703143A KR 19970703143 A KR19970703143 A KR 19970703143A KR 970707582 A KR970707582 A KR 970707582A
Authority
KR
South Korea
Prior art keywords
groove isolation
semiconductor device
latent active
isolation region
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019970703143A
Other languages
English (en)
Korean (ko)
Inventor
피터 케이. 문
아난다 지 사랑기
티모시 엘. 디터
Original Assignee
카알 실버맨
인텔 코퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 카알 실버맨, 인텔 코퍼레이션 filed Critical 카알 실버맨
Publication of KR970707582A publication Critical patent/KR970707582A/ko
Ceased legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D7/00—Details of apparatus for cutting, cutting-out, stamping-out, punching, perforating, or severing by means other than cutting
    • B26D7/08—Means for treating work or cutting member to facilitate cutting
    • B26D7/088—Means for treating work or cutting member to facilitate cutting by cleaning or lubricating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
    • B26F3/00—Severing by means other than cutting; Apparatus therefor
    • B26F3/002—Precutting and tensioning or breaking
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65C—LABELLING OR TAGGING MACHINES, APPARATUS, OR PROCESSES
    • B65C9/00—Details of labelling machines or apparatus
    • B65C9/08—Label feeding
    • B65C9/18—Label feeding from strips, e.g. from rolls
    • B65C9/1896—Label feeding from strips, e.g. from rolls the labels being torn or burst from a strip
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
    • B65H35/00—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers
    • B65H35/10—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers from or with devices for breaking partially-cut or perforated webs, e.g. bursters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Life Sciences & Earth Sciences (AREA)
  • Forests & Forestry (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
KR1019970703143A 1994-11-10 1995-11-13 기판의 지형을 수정함으로써 기판상에 평면에 형성하는 방법(forming a planar surface over a substrate by modifying the topography of the substrate) Ceased KR970707582A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33700094A 1994-11-10 1994-11-10
US08/337,000 1994-11-10

Publications (1)

Publication Number Publication Date
KR970707582A true KR970707582A (ko) 1997-12-01

Family

ID=23318670

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970703143A Ceased KR970707582A (ko) 1994-11-10 1995-11-13 기판의 지형을 수정함으로써 기판상에 평면에 형성하는 방법(forming a planar surface over a substrate by modifying the topography of the substrate)

Country Status (7)

Country Link
EP (1) EP0791227A4 (https=)
JP (1) JPH10512098A (https=)
KR (1) KR970707582A (https=)
CN (1) CN1171166A (https=)
AU (1) AU4235196A (https=)
TW (1) TW299458B (https=)
WO (1) WO1996015552A1 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665633A (en) 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
US5885856A (en) * 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
DE19703611A1 (de) * 1997-01-31 1998-08-06 Siemens Ag Anwendungsspezifisches integriertes Halbleiterprodukt mit Dummy-Elementen
JP3638778B2 (ja) 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP2006128709A (ja) * 1997-03-31 2006-05-18 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP5600280B2 (ja) * 1997-03-31 2014-10-01 ルネサスエレクトロニクス株式会社 半導体集積回路装置
EP0939432A1 (de) * 1998-02-17 1999-09-01 Siemens Aktiengesellschaft Verfahren zum Entwurf einer Maske zur Herstellung eines Dummygebiets in einem Isolationsgrabengebiet zwischen elektrisch aktiven Gebieten einer mikroelektronischen Vorrichtung
JP2000124305A (ja) 1998-10-15 2000-04-28 Mitsubishi Electric Corp 半導体装置
JP2000340529A (ja) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体装置
US6396158B1 (en) 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
JP4307664B2 (ja) 1999-12-03 2009-08-05 株式会社ルネサステクノロジ 半導体装置
US6459156B1 (en) 1999-12-22 2002-10-01 Motorola, Inc. Semiconductor device, a process for a semiconductor device, and a process for making a masking database
JP4767390B2 (ja) * 2000-05-19 2011-09-07 エルピーダメモリ株式会社 Ｄｒａｍ
US6614062B2 (en) * 2001-01-17 2003-09-02 Motorola, Inc. Semiconductor tiling structure and method of formation
US6611045B2 (en) 2001-06-04 2003-08-26 Motorola, Inc. Method of forming an integrated circuit device using dummy features and structure thereof
US6989229B2 (en) 2003-03-27 2006-01-24 Freescale Semiconductor, Inc. Non-resolving mask tiling method for flare reduction
JP4987254B2 (ja) 2005-06-22 2012-07-25 株式会社東芝 半導体装置の製造方法
FR2923914B1 (fr) 2007-11-21 2010-01-08 Commissariat Energie Atomique Dispositif pour mesures d'epaisseur et de resistivite carree de lignes d'interconnexions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186342A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6015944A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd 半導体装置
JPS6392042A (ja) * 1986-10-06 1988-04-22 Nec Corp 半導体装置の製造方法
JPS63240045A (ja) * 1987-03-27 1988-10-05 Matsushita Electric Ind Co Ltd 半導体装置
JP2580787B2 (ja) * 1989-08-24 1997-02-12 日本電気株式会社 半導体装置
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
DE69232648T2 (de) * 1991-11-29 2003-02-06 Sony Corp., Tokio/Tokyo Verfahren zur Herstellung einer Grabenisolation mittels eines Polierschritts und Herstellungsverfahren für eine Halbleitervorrichtung
JPH05258017A (ja) * 1992-03-11 1993-10-08 Fujitsu Ltd 半導体集積回路装置及び半導体集積回路装置の配線レイアウト方法
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
US5265378A (en) * 1992-07-10 1993-11-30 Lsi Logic Corporation Detecting the endpoint of chem-mech polishing and resulting semiconductor device
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers

Also Published As

Publication number Publication date
CN1171166A (zh) 1998-01-21
EP0791227A1 (en) 1997-08-27
JPH10512098A (ja) 1998-11-17
TW299458B (https=) 1997-03-01
EP0791227A4 (en) 1998-04-01
AU4235196A (en) 1996-06-06
WO1996015552A1 (en) 1996-05-23

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