AU4235196A - Forming a planar surface over a substrate by modifying the topography of the substrate - Google Patents

Forming a planar surface over a substrate by modifying the topography of the substrate

Info

Publication number
AU4235196A
AU4235196A AU42351/96A AU4235196A AU4235196A AU 4235196 A AU4235196 A AU 4235196A AU 42351/96 A AU42351/96 A AU 42351/96A AU 4235196 A AU4235196 A AU 4235196A AU 4235196 A AU4235196 A AU 4235196A
Authority
AU
Australia
Prior art keywords
substrate
topography
modifying
forming
planar surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU42351/96A
Other languages
English (en)
Inventor
Timothy L Deeter
Peter K Moon
Ananda G Sarangi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU4235196A publication Critical patent/AU4235196A/en
Abandoned legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D7/00—Details of apparatus for cutting, cutting-out, stamping-out, punching, perforating, or severing by means other than cutting
    • B26D7/08—Means for treating work or cutting member to facilitate cutting
    • B26D7/088—Means for treating work or cutting member to facilitate cutting by cleaning or lubricating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
    • B26F3/00—Severing by means other than cutting; Apparatus therefor
    • B26F3/002—Precutting and tensioning or breaking
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65C—LABELLING OR TAGGING MACHINES, APPARATUS, OR PROCESSES
    • B65C9/00—Details of labelling machines or apparatus
    • B65C9/08—Label feeding
    • B65C9/18—Label feeding from strips, e.g. from rolls
    • B65C9/1896—Label feeding from strips, e.g. from rolls the labels being torn or burst from a strip
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
    • B65H35/00—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers
    • B65H35/10—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers from or with devices for breaking partially-cut or perforated webs, e.g. bursters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Life Sciences & Earth Sciences (AREA)
  • Forests & Forestry (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AU42351/96A 1994-11-10 1995-11-13 Forming a planar surface over a substrate by modifying the topography of the substrate Abandoned AU4235196A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US337000 1989-04-12
US33700094A 1994-11-10 1994-11-10
PCT/US1995/014681 WO1996015552A1 (en) 1994-11-10 1995-11-13 Forming a planar surface over a substrate by modifying the topography of the substrate

Publications (1)

Publication Number Publication Date
AU4235196A true AU4235196A (en) 1996-06-06

Family

ID=23318670

Family Applications (1)

Application Number Title Priority Date Filing Date
AU42351/96A Abandoned AU4235196A (en) 1994-11-10 1995-11-13 Forming a planar surface over a substrate by modifying the topography of the substrate

Country Status (7)

Country Link
EP (1) EP0791227A4 (https=)
JP (1) JPH10512098A (https=)
KR (1) KR970707582A (https=)
CN (1) CN1171166A (https=)
AU (1) AU4235196A (https=)
TW (1) TW299458B (https=)
WO (1) WO1996015552A1 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665633A (en) 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
US5885856A (en) * 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
DE19703611A1 (de) * 1997-01-31 1998-08-06 Siemens Ag Anwendungsspezifisches integriertes Halbleiterprodukt mit Dummy-Elementen
JP3638778B2 (ja) 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP2006128709A (ja) * 1997-03-31 2006-05-18 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP5600280B2 (ja) * 1997-03-31 2014-10-01 ルネサスエレクトロニクス株式会社 半導体集積回路装置
EP0939432A1 (de) * 1998-02-17 1999-09-01 Siemens Aktiengesellschaft Verfahren zum Entwurf einer Maske zur Herstellung eines Dummygebiets in einem Isolationsgrabengebiet zwischen elektrisch aktiven Gebieten einer mikroelektronischen Vorrichtung
JP2000124305A (ja) 1998-10-15 2000-04-28 Mitsubishi Electric Corp 半導体装置
JP2000340529A (ja) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体装置
US6396158B1 (en) 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
JP4307664B2 (ja) 1999-12-03 2009-08-05 株式会社ルネサステクノロジ 半導体装置
US6459156B1 (en) 1999-12-22 2002-10-01 Motorola, Inc. Semiconductor device, a process for a semiconductor device, and a process for making a masking database
JP4767390B2 (ja) * 2000-05-19 2011-09-07 エルピーダメモリ株式会社 Ｄｒａｍ
US6614062B2 (en) * 2001-01-17 2003-09-02 Motorola, Inc. Semiconductor tiling structure and method of formation
US6611045B2 (en) 2001-06-04 2003-08-26 Motorola, Inc. Method of forming an integrated circuit device using dummy features and structure thereof
US6989229B2 (en) 2003-03-27 2006-01-24 Freescale Semiconductor, Inc. Non-resolving mask tiling method for flare reduction
JP4987254B2 (ja) 2005-06-22 2012-07-25 株式会社東芝 半導体装置の製造方法
FR2923914B1 (fr) 2007-11-21 2010-01-08 Commissariat Energie Atomique Dispositif pour mesures d'epaisseur et de resistivite carree de lignes d'interconnexions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186342A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6015944A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd 半導体装置
JPS6392042A (ja) * 1986-10-06 1988-04-22 Nec Corp 半導体装置の製造方法
JPS63240045A (ja) * 1987-03-27 1988-10-05 Matsushita Electric Ind Co Ltd 半導体装置
JP2580787B2 (ja) * 1989-08-24 1997-02-12 日本電気株式会社 半導体装置
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
DE69232648T2 (de) * 1991-11-29 2003-02-06 Sony Corp., Tokio/Tokyo Verfahren zur Herstellung einer Grabenisolation mittels eines Polierschritts und Herstellungsverfahren für eine Halbleitervorrichtung
JPH05258017A (ja) * 1992-03-11 1993-10-08 Fujitsu Ltd 半導体集積回路装置及び半導体集積回路装置の配線レイアウト方法
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
US5265378A (en) * 1992-07-10 1993-11-30 Lsi Logic Corporation Detecting the endpoint of chem-mech polishing and resulting semiconductor device
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers

Also Published As

Publication number Publication date
CN1171166A (zh) 1998-01-21
EP0791227A1 (en) 1997-08-27
KR970707582A (ko) 1997-12-01
JPH10512098A (ja) 1998-11-17
TW299458B (https=) 1997-03-01
EP0791227A4 (en) 1998-04-01
WO1996015552A1 (en) 1996-05-23

Similar Documents

Publication Publication Date Title
AU4235196A (en) Forming a planar surface over a substrate by modifying the topography of the substrate
AU4242393A (en) Method of enhancing the visibility of diffraction pattern surface embossment
AU683194B2 (en) Process useful for altering the permeability of a hydrocarbon-bearing formation
AU1270397A (en) Surface pattern
AU7460798A (en) A process for the manufacturing of a decorative laminate, a decorative laminate obtained by the process and use thereof
AU2360897A (en) Method of producing opaque adherent coating on the surface of substantially hydrated cemetitious substrate
AU616101B2 (en) Sprayable surface disinfectant
AU2105792A (en) Surface coating member
AU6355996A (en) Surface pattern
AU7784794A (en) Process for the galvanic application of a surface coating
AU698700B2 (en) A cleaner for a submerged surface
EP0604075A3 (en) Production of a carrier with a hard coating.
AU3810495A (en) Process for the manufacture of n-phosphonomethylglycine
AU6439694A (en) Cultivation substrate
AU6349394A (en) Pipewrap having a solid primer-adhesive layer
AU3783595A (en) A surface covering
GB9625363D0 (en) Method for planarizing the surface of a wafer
AU4174196A (en) Process for the preparation of a pharmacologically active chemical combination
AU5886899A (en) A process for the production of a laminated film
AU6574594A (en) Forming a hard layer on a substrate
USD367717S (en) Resilient tile
AU2625995A (en) Utility surface
AU8535698A (en) A process for the preparation of diacerein
AU2211800A (en) Combination cmp-etch method for forming a thin planar layer over the surface of a device
USD413763S (en) Surface pattern for cookware