AU4235196A - Forming a planar surface over a substrate by modifying the topography of the substrate - Google Patents
Forming a planar surface over a substrate by modifying the topography of the substrateInfo
- Publication number
- AU4235196A AU4235196A AU42351/96A AU4235196A AU4235196A AU 4235196 A AU4235196 A AU 4235196A AU 42351/96 A AU42351/96 A AU 42351/96A AU 4235196 A AU4235196 A AU 4235196A AU 4235196 A AU4235196 A AU 4235196A
- Authority
- AU
- Australia
- Prior art keywords
- substrate
- topography
- modifying
- forming
- planar surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B26—HAND CUTTING TOOLS; CUTTING; SEVERING
- B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
- B26D7/00—Details of apparatus for cutting, cutting-out, stamping-out, punching, perforating, or severing by means other than cutting
- B26D7/08—Means for treating work or cutting member to facilitate cutting
- B26D7/088—Means for treating work or cutting member to facilitate cutting by cleaning or lubricating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B26—HAND CUTTING TOOLS; CUTTING; SEVERING
- B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
- B26F3/00—Severing by means other than cutting; Apparatus therefor
- B26F3/002—Precutting and tensioning or breaking
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65C—LABELLING OR TAGGING MACHINES, APPARATUS, OR PROCESSES
- B65C9/00—Details of labelling machines or apparatus
- B65C9/08—Label feeding
- B65C9/18—Label feeding from strips, e.g. from rolls
- B65C9/1896—Label feeding from strips, e.g. from rolls the labels being torn or burst from a strip
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
- B65H35/00—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers
- B65H35/10—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers from or with devices for breaking partially-cut or perforated webs, e.g. bursters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US337000 | 1989-04-12 | ||
US33700094A | 1994-11-10 | 1994-11-10 | |
PCT/US1995/014681 WO1996015552A1 (en) | 1994-11-10 | 1995-11-13 | Forming a planar surface over a substrate by modifying the topography of the substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
AU4235196A true AU4235196A (en) | 1996-06-06 |
Family
ID=23318670
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU42351/96A Abandoned AU4235196A (en) | 1994-11-10 | 1995-11-13 | Forming a planar surface over a substrate by modifying the topography of the substrate |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0791227A4 (en) |
JP (1) | JPH10512098A (en) |
KR (1) | KR970707582A (en) |
CN (1) | CN1171166A (en) |
AU (1) | AU4235196A (en) |
TW (1) | TW299458B (en) |
WO (1) | WO1996015552A1 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665633A (en) | 1995-04-06 | 1997-09-09 | Motorola, Inc. | Process for forming a semiconductor device having field isolation |
US5885856A (en) * | 1996-08-21 | 1999-03-23 | Motorola, Inc. | Integrated circuit having a dummy structure and method of making |
DE19703611A1 (en) * | 1997-01-31 | 1998-08-06 | Siemens Ag | Application-specific integrated semiconductor product with dummy elements |
JP3638778B2 (en) | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device and manufacturing method thereof |
JP5600280B2 (en) * | 1997-03-31 | 2014-10-01 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
JP2006128709A (en) * | 1997-03-31 | 2006-05-18 | Renesas Technology Corp | Semiconductor integrated circuit device and manufacturing method therefor |
EP0939432A1 (en) * | 1998-02-17 | 1999-09-01 | Siemens Aktiengesellschaft | Mask design method for manufacturing a dummy region in a trench isolation region between electrically active regions of a microelectronic device |
JP2000124305A (en) | 1998-10-15 | 2000-04-28 | Mitsubishi Electric Corp | Semiconductor device |
JP2000340529A (en) * | 1999-05-31 | 2000-12-08 | Mitsubishi Electric Corp | Semiconductor device |
US6396158B1 (en) | 1999-06-29 | 2002-05-28 | Motorola Inc. | Semiconductor device and a process for designing a mask |
JP4307664B2 (en) | 1999-12-03 | 2009-08-05 | 株式会社ルネサステクノロジ | Semiconductor device |
US6459156B1 (en) | 1999-12-22 | 2002-10-01 | Motorola, Inc. | Semiconductor device, a process for a semiconductor device, and a process for making a masking database |
JP4767390B2 (en) * | 2000-05-19 | 2011-09-07 | エルピーダメモリ株式会社 | DRAM |
US6614062B2 (en) * | 2001-01-17 | 2003-09-02 | Motorola, Inc. | Semiconductor tiling structure and method of formation |
US6611045B2 (en) * | 2001-06-04 | 2003-08-26 | Motorola, Inc. | Method of forming an integrated circuit device using dummy features and structure thereof |
US6989229B2 (en) | 2003-03-27 | 2006-01-24 | Freescale Semiconductor, Inc. | Non-resolving mask tiling method for flare reduction |
JP4987254B2 (en) | 2005-06-22 | 2012-07-25 | 株式会社東芝 | Manufacturing method of semiconductor device |
FR2923914B1 (en) * | 2007-11-21 | 2010-01-08 | Commissariat Energie Atomique | DEVICE FOR THICKNESS AND SQUARE RESISTIVITY MEASUREMENTS OF INTERCONNECTION LINES |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59186342A (en) * | 1983-04-06 | 1984-10-23 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS6015944A (en) * | 1983-07-08 | 1985-01-26 | Hitachi Ltd | Semiconductor device |
JPS6392042A (en) * | 1986-10-06 | 1988-04-22 | Nec Corp | Manufacture of semiconductor device |
JPS63240045A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JP2580787B2 (en) * | 1989-08-24 | 1997-02-12 | 日本電気株式会社 | Semiconductor device |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5498565A (en) * | 1991-11-29 | 1996-03-12 | Sony Corporation | Method of forming trench isolation having polishing step and method of manufacturing semiconductor device |
JPH05258017A (en) * | 1992-03-11 | 1993-10-08 | Fujitsu Ltd | Semiconductor integrated circuit device and wiring layout method for the same |
US5229316A (en) * | 1992-04-16 | 1993-07-20 | Micron Technology, Inc. | Semiconductor processing method for forming substrate isolation trenches |
US5265378A (en) * | 1992-07-10 | 1993-11-30 | Lsi Logic Corporation | Detecting the endpoint of chem-mech polishing and resulting semiconductor device |
US5278105A (en) * | 1992-08-19 | 1994-01-11 | Intel Corporation | Semiconductor device with dummy features in active layers |
-
1995
- 1995-10-20 TW TW084111123A patent/TW299458B/zh active
- 1995-11-13 CN CN95197102A patent/CN1171166A/en active Pending
- 1995-11-13 JP JP8516234A patent/JPH10512098A/en active Pending
- 1995-11-13 EP EP95940684A patent/EP0791227A4/en not_active Withdrawn
- 1995-11-13 AU AU42351/96A patent/AU4235196A/en not_active Abandoned
- 1995-11-13 WO PCT/US1995/014681 patent/WO1996015552A1/en not_active Application Discontinuation
- 1995-11-13 KR KR1019970703143A patent/KR970707582A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
TW299458B (en) | 1997-03-01 |
KR970707582A (en) | 1997-12-01 |
WO1996015552A1 (en) | 1996-05-23 |
EP0791227A1 (en) | 1997-08-27 |
CN1171166A (en) | 1998-01-21 |
EP0791227A4 (en) | 1998-04-01 |
JPH10512098A (en) | 1998-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU4235196A (en) | Forming a planar surface over a substrate by modifying the topography of the substrate | |
AU683194B2 (en) | Process useful for altering the permeability of a hydrocarbon-bearing formation | |
AU3663893A (en) | Surface remediator | |
AU9552898A (en) | Pattern formation | |
AU1985595A (en) | High vertical aspect ratio thin film structures | |
AU7460798A (en) | A process for the manufacturing of a decorative laminate, a decorative laminate obtained by the process and use thereof | |
AU6345896A (en) | Structured surface fastener | |
AU2360897A (en) | Method of producing opaque adherent coating on the surface of substantially hydrated cemetitious substrate | |
AU616101B2 (en) | Sprayable surface disinfectant | |
AU2001290486A1 (en) | A process for the manufacture of surface elements | |
AU2105792A (en) | Surface coating member | |
AU6355996A (en) | Surface pattern | |
AU698700B2 (en) | A cleaner for a submerged surface | |
AU7784794A (en) | Process for the galvanic application of a surface coating | |
EP0604075A3 (en) | Production of a hard coated substrate. | |
GB9625363D0 (en) | Method for planarizing the surface of a wafer | |
AU6574594A (en) | Forming a hard layer on a substrate | |
AU6349394A (en) | Pipewrap having a solid primer-adhesive layer | |
AU2625995A (en) | Utility surface | |
AU3783595A (en) | A surface covering | |
AU8535698A (en) | A process for the preparation of diacerein | |
AU2211800A (en) | Combination cmp-etch method for forming a thin planar layer over the surface of a device | |
AUPM967194A0 (en) | Surface modification of kaolinite | |
AU8429198A (en) | Surface modifying process | |
USD367717S (en) | Resilient tile |