JP5600280B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor integrated circuit device including a planarization process using a CMP (Chemical Mechanical Polishing) method in the manufacturing process. .

  As the minimum processing size of the semiconductor integrated circuit device decreases, it is necessary to improve the performance of the stepper, and the lens aperture diameter is increased and the exposure wavelength is shortened. As a result, the depth of focus of the exposure optical system becomes shallow, and slight unevenness on the surface to be processed becomes a problem. As a result, flattening of the surface to be processed has become an important technical problem in the device process. Moreover, the above flattening is not flattening for the purpose of relaxing the step shape required to prevent disconnection of the wiring formed on the step, but global flattening, that is, complete flattening is required. Is.

  Surface flattening techniques include self-flattening by applying SOG (Spin On Glass) film or low-melting glass coating and melting, heat treatment by glass flow, and CVD (Chemical Vapor Deposition) surface reaction mechanism. However, there are many cases where complete planarization, that is, global planarization cannot be performed due to surface conditions, conditions such as heat treatment to be applied, or restrictions on processing thereof. In view of this, the etch-back method and the CMP method are promising as a technique that enables practical flattening.

  Etch-back methods are known in which a photoresist is used as a sacrificial film, a film using an SOG film, a film using a self-planarizing CVD film, etc., but the process complexity, cost, and yield reduction due to particles are reduced. On the other hand, the CMP method has a relatively small number of problems that occur in the etch-back method, and a recognition that it is a generally excellent process in comparison with the etch-back method is generally being formed. In other words, the CMP method is considered most promising as a practical technique capable of realizing complete planarization.

  As examples in which the CMP technique is described in detail, for example, JP-A-7-74175 (Patent Document 1), JP-A-6-196551 (Patent Document 2), May 1, 1996, Published by Industrial Research Council, “Electronic Materials”, May 1996, p22 to p27 (Non-patent Document 1).

JP-A-7-74175 JP-A-6-196551

“Electronic Materials”, May 1996 issue, Industrial Research Committee, p22-p27

  However, in the process of studying the complete planarization technology of the device surface to which the CMP method is applied, the present inventor has recognized that there are the following problems, although it is not a known technology.

FIGS. 29A to 29D are cross-sectional views for explaining a planarization technique by a CMP method investigated by the present inventors. As a method of covering the wiring with an insulating film and flattening the insulating film, first, the wiring 102 is formed on the interlayer insulating film 101 (FIG. 29A), and then TEOS (Tetraethoxysilane: (C _2). A first insulating film 103 and a second insulating film 104 such as SOG are deposited by a plasma CVD method using H ₅ O) ₄ Si) or the like, and a recess is embedded (FIG. 29B), and a TEOS plasma CVD method or the like is performed. A third insulating film 105 is deposited (FIG. 29C), and the third insulating film 105 can be polished and planarized by CMP (FIG. 29D).

  At this time, the pattern of the wiring 102 focuses on whether or not the layout design based on the functional design and the logic design is in accordance with a normal layout rule, and the polishing characteristics in the CMP process are not particularly taken into consideration.

  Therefore, the wiring pattern is sparse and dense depending on the location, and in the above study drawing (FIG. 29D), the wiring 102 is densely formed in the portion A, and the wiring 102 is sparsely formed in other regions. The Rukoto.

  As described above, when the CMP polishing is performed in a state where the wiring 102 is sparse and dense, the surface of the third insulating film 105 cannot be completely planarized. An elevation difference of 2 to 0.7 μm occurs, and a large undulation remains on the surface.

  On the surface where such undulations exist, the process margin is lowered in the subsequent photolithography process or etching process, and it becomes difficult to cope with fine processing and high integration, thereby improving the reliability and yield of the semiconductor integrated circuit device. It cannot be improved.

  In addition, it is necessary to optimize process conditions in order to satisfactorily perform lithography and etching in a wavy state, and it is also necessary to optimize a CMP process in order to minimize waviness. There is also a problem that the start-up time of the mass production process is delayed by the period required for such optimization.

  Further, in the region where the wiring 102 is sparse, the space between the wirings 102 is not sufficiently embedded by the second insulating film 104, and the thickness of the third insulating film 105 has to be increased in order to completely fill such a recess. . As a result, there arises a problem that not only the process load such as the deposition time of the third insulating film 105 becomes longer, but also the polishing amount of the third insulating film 105 increases and the process load in the CMP process also increases. .

  An object of the present invention is to completely flatten the surface of a member after polishing by the CMP method.

  Another object of the present invention is to provide a technology capable of improving process margins in a photolithography process, an etching process, and the like, and capable of dealing with fine processing and high integration, and reliability of a semiconductor integrated circuit device and It is to improve the yield.

  Another object of the present invention is to facilitate process startup.

  Another object of the present invention is to reduce the polishing amount of a member to be polished by the CMP method, and to improve cost competitiveness by reducing the process load and shortening the process time.

  Another object of the present invention is to provide a method for designing a member pattern that can be completely flattened by a CMP method.

  Another object of the present invention is to suppress an increase in parasitic capacitance such as wiring caused by a measure for realizing complete flattening and to ensure the performance of a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A semiconductor integrated circuit device of the present invention covers a wiring constituting a semiconductor integrated circuit element formed on a main surface of a semiconductor substrate or on an interlayer insulating film, and covers the wiring, and is planarized by a CMP method. A semiconductor integrated circuit device having an insulating film including a coating, wherein the wiring layer in which the wiring is formed is formed of the same material as the wiring in a gap region formed at a distance between the wirings as an element A dummy wiring that does not function is formed.

  The semiconductor integrated circuit device according to the present invention includes a shallow trench formed in a main surface of a semiconductor substrate, an element isolation region in which an insulating film including a film planarized by a CMP method is embedded in the shallow trench, and an element isolation A semiconductor integrated circuit device including an active region of a semiconductor integrated circuit element separated by a region, wherein the semiconductor does not function as a semiconductor integrated circuit element in a void region of a semiconductor substrate formed at a distance between the active regions A dummy region on the main surface of the substrate is formed.

  According to such a semiconductor integrated circuit device, since the dummy wiring or the dummy area is formed in the gap region, the surface of the insulating film covering the wiring or the main surface of the semiconductor substrate is completely covered so that a sparse portion is not generated. It can be flattened.

  That is, when only the wiring or the active region (element constituent member) is formed without forming the dummy wiring or the dummy region (dummy member), a gap region having a large distance between the element constituent members is generated. When the insulating film is deposited while such a void region exists, the shape of the surface of the insulating film around the void region becomes an uneven shape that faithfully reflects the shape of the element constituent member. Such a concavo-convex shape becomes a factor inhibiting complete flattening as shown in FIG.

  Therefore, in the present invention, a dummy member is disposed in such a gap region, the uneven shape of the insulating film is relaxed, and the surface of the insulating film after CMP polishing is completely planarized.

  As described above, since the surface of the insulating film is completely planarized, the process margin can be increased in the subsequent photolithography process or etching process. As a result, the manufacturing yield of the semiconductor integrated circuit device can be improved, and the process can be performed. The raising time can be shortened.

  Examples of wiring include metal wiring formed on an interlayer insulating film, gate wiring of MISFET (Metal-Insulator-Semiconductor Field Effect Transistor), and bit line of DRAM (Dynamic Random Access Memory). Needless to say, the metal wiring and the gate wiring are not limited to those of a memory element such as a DRAM but also include a logic element. In particular, since the logic element wiring is generally a multilayer wiring of three or more layers, if the present invention is applied to such wiring, a remarkable effect can be obtained.

  (2) Further, in the semiconductor integrated circuit device of the present invention, in the semiconductor integrated circuit device described above, the distance between the dummy wiring and the members of the wiring, or the distance between the members of the dummy region and the active region is determined by lithography. Including a high-density member forming region that satisfies the condition that the minimum space width required from the resolution of the above and the height of the wiring or the depth of the shallow groove is not more than twice the area, and the area is 95% of the chip area That is all.

  Thus, by setting the distance between the dummy wiring and the wiring or the members of the dummy region and the active region to be twice or less the height of the wiring or the depth of the shallow groove, the insulating film formed on these members The pattern dependency of the member pattern does not occur in the CMP polishing rate, the CMP polishing rate becomes uniform, and the surface flatness of the insulating film can be made almost perfect.

  FIG. 30 is data showing the knowledge obtained by the inventor's experimental study, and is a graph showing the value of the variation of the CMP polishing amount with respect to the inter-pattern distance. The horizontal axis represents the distance between patterns normalized by the pattern height, and the vertical axis represents the CMP polishing amount of the insulating film on the pattern with respect to the reference pattern (solid pattern). As apparent from FIG. 30, even if the pattern is separated to about twice the pattern height, the CMP polishing amount of the insulating film does not change. That is, if the distance between the members of the dummy wiring and the wiring, or the dummy region and the active region is set to be twice or less the height of the wiring or the depth of the shallow groove, the CMP of the insulating film formed on these members is performed. The speed is constant regardless of the pattern, and the insulating film can be completely planarized.

  As described above, a region where complete planarization can be realized, that is, a high-density member forming region is preferable because the entire chip can be flattened as much as possible, but the entire chip area does not have to be a high-density member forming region. That is, a practically sufficiently flat surface can be obtained if the high-density member forming region capable of realizing complete planarization is 95% or more of the chip area.

  In addition, the condition that the interval between these members is equal to or larger than the minimum space width required from the resolution of lithography is that a processing space larger than the minimum processing dimension is required to perform member processing satisfactorily, By satisfying this condition, the wiring or dummy wiring, or the active region or dummy region can be processed satisfactorily. An example of the minimum space width is 0.2 μm when a KrF excimer laser is used as an exposure source.

  In the remaining 5% of the region that is not the high-density member forming region, the distance between the members of the dummy wiring and the wiring or the dummy region and the active region is not more than four times the height of the wiring or the depth of the shallow groove. It is preferable that they are arranged. As shown in FIG. 30, the insulating film in the region where the pattern interval is arranged at a distance not more than four times the height of the wiring or the depth of the shallow groove, that is, the low density member forming region is approximately twice as shown in FIG. Although the amount of polishing varies, the contribution of the low density member formation region is negligible because it is 5% or less of the chip area.

  In the semiconductor integrated circuit device of the present invention, in the semiconductor integrated circuit device, the dummy wiring or the dummy region has a width equal to or larger than the minimum line width required from the resolution of lithography, or the length is the minimum line width. The width and length of the dummy wiring or dummy region in the scribe region is equal to or less than the interval between the bonding pads. The minimum space width and minimum line width can be 0.2 μm, and the distance between bonding pads can be 10 μm.

  According to such a semiconductor integrated circuit device, the dummy wiring or the dummy region can be reliably processed by setting the width of the dummy wiring or the dummy region to be equal to or larger than the minimum line width required from the resolution of lithography. By setting the length of the dummy wiring or dummy area to be twice or more the minimum line width, the resolution of these members can be reliably maintained. That is, there is a possibility that the pattern having the minimum processing dimension width and length cannot be accurately resolved. However, in the present invention, the length of the dummy wiring or the dummy region is doubled to avoid the fear. be able to. The width and length of the dummy wiring or dummy area is 30 μm or less, but 20 μm or less is frequently used, and preferably 10 μm or less.

  Further, by setting the width and length of the dummy wiring or dummy region to 30 μm or less, it is possible to reduce the parasitic capacitance of the wiring and the like, and to reduce the short-circuit defect between the bonding pads. That is, if the width or length of the dummy wiring or dummy area is increased, the dummy members are increased, and the parasitic capacitance of the wiring functioning as a semiconductor integrated circuit element is increased, so that the high-speed response performance of the semiconductor integrated circuit device. However, if the width or length is 30 μm or less, it is possible to suppress parasitic capacitance such as wiring to such an extent that no practical problem occurs. Further, when the dummy wiring is arranged in the scribe region, the chips generated by the scribe may become conductive dust. However, even if it is conductive dust, the portion that can be short-circuited by that is limited to between the bonding pads, so if the width and length of the dummy wiring are less than or equal to the distance between the bonding pads, Even if it becomes conductive dust, there is no short circuit defect. These effects can prevent the performance and yield of the semiconductor integrated circuit device from being lowered.

  In the semiconductor integrated circuit device of the present invention, dummy wirings or dummy regions are also formed in the scribe region.

  According to such a semiconductor integrated circuit device, complete flatness can be secured even in the scribe region, and complete flatness of the entire wafer can be realized.

  In the semiconductor integrated circuit device of the present invention, the pattern density of wiring composed of dummy wirings and wirings or the pattern density of regions composed of dummy regions and active regions is made substantially uniform over the entire region of the semiconductor substrate.

  Even with such a semiconductor integrated circuit device, complete flatness of the insulating film on these patterns can be realized. That is, as described above, the flatness of the insulating film on the pattern is hindered because there is nonuniformity in the density of the pattern, so that the nonuniformity in the density of the pattern does not occur. The uniformity of the insulating film can also be improved by providing a dummy member.

  (3) Further, the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device described above, wherein the dummy wiring is the same as the bonding pad portion provided on the semiconductor substrate or the marker portion for photolithography. The wiring layer is not formed around the bonding pad portion or the marker portion.

  According to such a semiconductor integrated circuit device, automatic detection of a bonding pad during wire bonding and automatic detection of a marker used for mask alignment during photolithography can be performed smoothly. That is, when dummy members of the same material are formed around the bonding pads or markers, there is a possibility that the dummy members become noise and are not detected well when the bonding pads or markers are detected. There is no such fear in the present invention.

  The region where the dummy wiring is not formed can be a region 20 μm from the bonding pad portion or a region 60 μm from the marker portion.

  In addition, the semiconductor integrated circuit device of the present invention has a silicon oxide film formed by an SOG method or a high-density plasma CVD method, a BPSG (Boron-doped Phospho-Silicate Glass) film or a PSG formed by a reflow method as an insulating film. (Phospho-Silicate Glass) film or polysilazane film may be included.

  According to such a semiconductor integrated circuit device, the silicon oxide film formed by the SOG method or the high density plasma CVD method, the BPSG film, the PSG film or the polysilazane film formed by the reflow method has excellent step coverage, and the concave portion Therefore, the recess formed by the wiring and the dummy wiring or the active region and the dummy region can be satisfactorily filled, and the thickness of the insulating film polished by the CMP method can be reduced. Such thinning of the CMP polishing film not only reduces the load of the CMP polishing film deposition process, but also can reduce the load of the CMP process, thereby reducing the cost competitiveness of the semiconductor integrated circuit device such as shortening the process time. It can also be improved.

  A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device as described above, wherein (a) a conductive film containing polycrystalline silicon or metal is deposited on a main surface or an interlayer insulating film of a semiconductor substrate. (B) forming a wiring and a dummy wiring by patterning the conductive film, and (b) forming an upper layer of the wiring and the dummy wiring including the inner surface of the recess formed by the wiring and the dummy wiring by an SOG method or a high-density plasma CVD method. Depositing a first insulating film made of the formed silicon oxide film, a BPSG film or a PSG film formed by a reflow method, or a polysilazane film, and embedding a recess; (c) a second on the first insulating film; And (d) a step of polishing the surface of the second insulating film by a CMP method, and the thickness of the second insulating film is set to the surface of the first insulating film. It is an adequate thickness to planarize irregularities.

  According to such a method of manufacturing a semiconductor integrated circuit device, the deposited film thickness of the second insulating film can be reduced, and not only the deposition time of the second insulating film is shortened but also the first polishing process in the CMP polishing step. The amount of polishing of the insulating film 2 can also be reduced. For this reason, while the process itself follows the conventional process, the process time can be shortened, the process load can be reduced, and the cost competitiveness of the semiconductor integrated circuit device can be improved.

  That is, in the manufacturing method of the present invention, the recess formed by the wiring and the dummy wiring is formed by forming a silicon oxide film formed by the SOG method or the high-density plasma CVD method, a BPSG film or PSG film formed by the reflow method, or a polysilazane film. Therefore, the unevenness remaining on the surface of the second insulating film is relaxed compared to the unevenness before the film is formed. Therefore, the film thickness of the second insulating film is set to a film thickness sufficient to flatten the unevenness of the surface of the first insulating film, that is, the surface of the second insulating film is sufficiently formed even with a small film thickness. Flattening is possible.

  (4) A hard pad can be used for this CMP polishing.

  Further, the unevenness of the surface caused by the wiring and the dummy wiring can be substantially flattened by the first and second insulating films, and the polishing by the CMP method can be used only for the surface finishing polishing. The polishing means used for this surface finishing is not limited to the CMP method, and other polishing methods such as dry belt polishing and lapping may be used.

  According to another aspect of the present invention, there is provided a semiconductor integrated circuit device manufacturing method comprising: (a) depositing a silicon nitride film on a main surface of a semiconductor substrate and forming silicon in regions other than the active region and the dummy region; Forming a shallow groove by patterning the nitride film and the semiconductor substrate; (b) depositing an insulating film made of a silicon oxide film on the semiconductor substrate including the inner surface of the shallow groove and the wiring and the silicon nitride film; And (c) a step of polishing the insulating film by a CMP method to expose the silicon nitride film.

  According to such a manufacturing method of a semiconductor integrated circuit device, since the dummy region is formed also in the element isolation region, dishing of the element isolation region, that is, depression is prevented, and the surface of the semiconductor substrate can be completely planarized. In addition, since a silicon nitride film having a slower CMP polishing rate than the silicon oxide film is formed between the insulating film as the CMP polishing film and the active region of the semiconductor substrate, the silicon nitride film serves as a stopper layer for CMP polishing. Furthermore, it is possible to ensure complete flatness.

  The slurry used in the CMP method in the step (c) is an alkaline slurry using silicon oxide as an abrasive, and after the step (c), the insulating film formed in the shallow groove is etched by wet etching or dry etching. And a step of making the height of the surface of the insulating film equal to or lower than the main surface of the semiconductor substrate. When the slurry is an alkaline slurry using silicon oxide as an abrasive, the polishing rate ratio between the silicon oxide film and the silicon nitride film is 3 to 4 to 1, and it is necessary to increase the thickness of the silicon nitride film. is there. In such a case, the relationship between the height of the main surface of the semiconductor substrate after removing the silicon nitride film, that is, the active region, and the height of the silicon oxide film as the element isolation region is higher in the silicon oxide film. Therefore, the silicon oxide film is further etched by wet etching or dry etching so that the surface height of the insulating film is the same as or lower than the main surface of the semiconductor substrate. This makes it possible to perform fine gate processing.

  Further, the slurry used in the CMP method in the step (c) can be a slurry using cerium oxide as an abrasive. In this case, the polishing rate ratio between the silicon oxide film and the silicon nitride film is 30 to 50: 1, and it is not necessary to increase the thickness of the silicon nitride film. Therefore, the film thickness of the silicon nitride film can be negligible in the process, for example, 50 nm or less, and etching of the silicon oxide film after removing the silicon nitride film is not necessary.

  (5). The design method of the present invention is a design method including a step of generating a mask pattern of a mask used for processing a member constituting a semiconductor integrated circuit element, and the mask pattern includes a member member pattern, A dummy condition that is not arranged in the dummy placement prohibition region, and a first condition in which a pattern space between the member pattern and the dummy pattern is a minimum space width required from the resolution of lithography or 0.2 μm or more, A second condition in which the pattern interval is not more than twice the height of the member in a region of 95% or more of the chip area, and is not more than four times the height of the member in a region of 5% or less of the chip area; Third condition that the width of the dummy pattern is the minimum line width required from the resolution of lithography or 0.2 μm or more, the width of the dummy pattern is half A fourth condition in which the interval between bonding pads provided in the body integrated circuit device or 10 μm or less, a fifth condition in which the length of the dummy pattern is twice the minimum line width or 0.2 μm or more, and the dummy pattern The mask pattern is generated such that the length satisfies any of the conditions between the bonding pads and the sixth condition of 10 μm or less.

  According to such a design method, it is possible to design a mask having a member pattern necessary for manufacturing the semiconductor integrated circuit device. Each of the above conditions is for realizing the effect of the semiconductor integrated circuit device described above.

  Needless to say, the dummy pattern can also be arranged in the scribe region of the semiconductor substrate.

  In addition, the dummy placement prohibition region is in a range of 20 μm from the end of the pattern to be a bonding pad, in a range of 60 μm from the end of the pattern to be a photolithography marker, in a range of 0.5 μm from the region in which the connection hole is formed, Alternatively, it can be a fuse region. In such a case, it is easy to detect a bonding pad or a marker for mask alignment during wire bonding or photolithography, and wiring between different layers or a connection hole between the wiring and the semiconductor substrate can be formed.

  Further, in the case where the member is a metal wiring formed in substantially the same layer as the storage capacitor formed in the upper layer of the bit line, the region where the storage capacitor is formed can be set as a dummy placement prohibited region. In such a case, the first metal wiring layer can be formed in the same layer as the storage capacitor of the DRAM, and a dummy wiring can be arranged in the region of the first metal wiring layer.

  When the member is an active region formed on the main surface of the semiconductor substrate, the region where the gate wiring is formed on the main surface of the semiconductor substrate can be a dummy arrangement prohibition region. In such a case, since a dummy region is not formed under the gate wiring, the capacitance between the gate wiring and the semiconductor substrate can be reduced. That is, the dummy region on the main surface of the semiconductor substrate apparently has the same structure as the active region of the semiconductor substrate. Therefore, when the gate wiring is formed on the dummy region, the capacity of the gate wiring increases. For this reason, no dummy region is formed under the gate wiring. Thereby, performance such as high-speed response performance of the semiconductor integrated circuit device can be improved.

  In the design method of the present invention, the dummy pattern is arranged so that the stray capacitance of the member increased by the dummy member formed by the dummy pattern is minimized. Thereby, performance such as high-speed response performance of the semiconductor integrated circuit device can be improved. Such an arrangement can be performed by satisfying the conditions of the design method, and by optimizing so that the area of the dummy pattern is minimized and the number of dummy patterns is minimized. Further, such optimization can be automatically calculated by an information processing apparatus such as a computer that generates a layout pattern.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The member surface after polishing by the CMP method can be completely flattened.

  A process margin in a photolithography process, an etching process, and the like can be improved, and microfabrication and high integration can be dealt with. Thus, reliability and yield of a semiconductor integrated circuit device can be improved.

  Process startup can be facilitated.

  The amount of polishing of the member polished by the CMP method can be reduced, and the cost competitiveness can be improved by reducing the process load and the process time.

  It is possible to provide a method for designing a member pattern that can be completely planarized by the CMP method.

  It is possible to suppress an increase in parasitic capacitance such as wiring caused by measures for realizing complete planarization, and to secure the performance of the semiconductor integrated circuit device.

1 is a cross-sectional view illustrating an example of a logic integrated circuit device according to a first embodiment. FIG. 2 is a main part plan view showing the arrangement of wirings and dummy wirings in a first wiring layer in FIG. 1. (B) is a top view explaining the layout rule applied to arrangement | positioning of wiring and dummy wiring, (a) is sectional drawing of the direction along the AA in FIG.3 (b). It is sectional drawing which expanded and showed the wiring part in FIG. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view illustrating an example of a logic integrated circuit device according to a second embodiment. FIG. 10 is a plan view showing the arrangement of wirings and dummy wirings in a fifth wiring layer in the second embodiment. FIG. 6 is a cross-sectional view illustrating an example of a logic integrated circuit device according to a second embodiment. (A) And (b) is the top view which showed the other example of the logic integrated circuit device of Embodiment 2. FIG. FIG. 10 is a cross-sectional view showing an example of a DRAM of a third embodiment. It is a graph which shows the relationship between a pattern dimension and the focal depth of lithography. FIG. 11 is a cross-sectional view showing an example of a method for manufacturing the DRAM of Embodiment 3 in the order of steps. FIG. 11 is a cross-sectional view showing an example of a method for manufacturing the DRAM of Embodiment 3 in the order of steps. FIG. 11 is a cross-sectional view showing an example of a method for manufacturing the DRAM of Embodiment 3 in the order of steps. FIG. 11 is a cross-sectional view showing an example of a method for manufacturing the DRAM of Embodiment 3 in the order of steps. FIG. 10 is a plan view showing an example of a manufacturing method of the DRAM of Embodiment 3 in the order of steps. FIG. 6 is a cross-sectional view showing an example of a semiconductor integrated circuit device according to a fourth embodiment. FIG. 6 is a plan view showing an example of a semiconductor integrated circuit device according to a fourth embodiment. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing the semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing the semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing the semiconductor integrated circuit device of the fourth embodiment in the order of steps. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing the semiconductor integrated circuit device of the fourth embodiment in the order of steps. (A)-(d) is sectional drawing for demonstrating the planarization technique by CMP method which this inventor examined. It is the graph which showed the value of variation of CMP polish amount with respect to distance between patterns. FIG. 6 is a plan view showing an example of a semiconductor integrated circuit device according to a fourth embodiment. It is sectional drawing which showed an example of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 33 is a plan view of relevant parts of the semiconductor integrated circuit device shown in FIG. 32. FIG. 33 is a plan view of relevant parts of the semiconductor integrated circuit device shown in FIG. 32.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a sectional view showing an example of a logic integrated circuit device which is an embodiment of a semiconductor integrated circuit device of the present invention. In FIG. 1, A is a scribe area, B is a pad / peripheral circuit area, and C is a logic circuit area.

  In the logic integrated circuit device according to the first embodiment, a shallow trench (Shallow trench) 2 is formed on the main surface of a semiconductor substrate 1, and an element isolation region 3 in which a silicon oxide film as an insulating film is embedded in the shallow trench 2 is formed. It is what you have. The element isolation region 3 defines an active region 4 formed on the main surface of the semiconductor substrate 1. Here, a shallow trench element isolation structure is exemplified as element isolation, but an element isolation structure by a field insulating film formed by a LOCOS (Local Oxidation of Silicon) method may be used. Although not shown here, p-type and n-type well regions may be formed on the main surface of the semiconductor substrate.

  A MISFET is formed in the active region 4. On the main surface of the semiconductor substrate, a gate wiring 6 is formed via a gate insulating film 5 of MISFET. The gate insulating film 5 can be a silicon oxide film formed by, for example, a thermal oxidation method, and the gate wiring 6 can be a polycrystalline silicon film formed by, for example, a CVD method. A silicide layer for reducing electric resistance may be formed on the surface of the polycrystalline silicon film.

  A part of the gate wiring 6 is formed so as to extend on the element isolation region 3, and the other part becomes the gate electrode 7 of the MISFET Q 1 formed in the active region 4 of the semiconductor substrate 1. Impurity semiconductor regions 8 are formed in the active region 4 which is the main surface of the semiconductor substrate 1 on both sides of the gate electrode 7. The impurity semiconductor region 8 functions as a source / drain region of the MISFET Q1, and can also be a so-called LDD (Lightly Doped Drain). Further, side wall spacers 8 b are formed on the side surfaces of the gate wiring 6. Sidewall spacer 8b can be, for example, a silicon oxide film or a silicon nitride film.

  The MISFET Q1 formed in the logic circuit region C functions as an active element of the logic circuit. Although not shown, the MISFET formed in the pad / peripheral circuit region B functions as an active element of the peripheral circuit. The MISFET is exemplified as the transistor formed in the logic circuit region C and the pad / peripheral circuit region B. However, a bipolar transistor or a Bi-CMOS transistor may be used.

  The gate wiring 6 is covered with an interlayer insulating film 9. On the interlayer insulating film 9, a wiring 10 composed of a first wiring layer and a dummy wiring 11 are formed.

  The interlayer insulating film 9 can be a silicon oxide film such as a PSG film, a BPSG film, or an SOG film. Further, in order to prevent diffusion of impurities, a laminated film with a TEOS silicon oxide film or the like can be used. The surface of the interlayer insulating film 9 is preferably flattened by a CMP method or an etch back method.

  The wiring 10 and the dummy wiring 11 are made of the same material and are formed in the same process (same layer). Examples of the material include metals such as aluminum (Al) and copper (Cu), but may be a polycrystalline silicon film doped with impurities at a high concentration. In the case of a polycrystalline silicon film, the surface may be silicided.

  FIG. 2 is a plan view showing the arrangement of the wiring 10 and the dummy wiring 11 in the first layer.

  The dummy wiring 11 is formed in a region (gap region) where the interval between the wirings 10 is wide. As a result, the dummy wirings 11 are evenly spread over the area where the wirings 10 are not formed, and the distance between the members consisting of the dummy wirings 11 and the wirings 10 is narrow, and the dummy wirings 11 are arranged so as to be densely filled. It will be.

  The dummy wiring 11 is also formed in the scribe area A. Thereby, the flatness of the insulating film 12 to be described later is ensured over the entire surface of the semiconductor substrate 1. The width and length of the dummy wiring 11 formed in the scribe region A are configured to be equal to or less than the distance between the bonding pads.

  FIG. 3B is a plan view for explaining a layout rule applied to the arrangement of the wiring 10 and the dummy wiring 11, and FIG. 3A is a cross section taken along the line AA in FIG. FIG.

  The distance S between the wiring 10 and the dummy wiring 11 and the member interval S, which is the distance between the dummy wirings 11, is less than twice the wiring height H of the dummy wiring 11 and the wiring 10. Thus, by setting the member interval S to be equal to or less than twice the wiring height H, the CMP polishing amount of the insulating film 12 can be made uniform as described with reference to FIG. The surface can be completely flattened. However, in the region of 5% or less of the chip area, the member interval S is allowed to be 4 times or less of the wiring height H. In this case, the variation in the polishing amount of the insulating film 12 is about twice, but since the area is 5% or less of the chip area, it can be ignored as a whole, and the entire insulating film 12 is almost flat. it can.

  In addition, the member interval S needs to be greater than the minimum space width required by the lithography tool. Under these conditions, reliable processing of the wiring 10 and the dummy wiring 11 is ensured, and the member can be processed as designed. An example of the minimum space width is 0.2 μm in the case of an exposure apparatus using a KrF excimer laser as a light source.

  The width a of the dummy wiring 11 is not less than the minimum line width required by the lithography tool. By making the width a equal to or greater than the minimum line width, the processing of the dummy wiring 11 can be ensured. In the scribe region, the width a of the dummy wiring 11 is set to be equal to or smaller than the distance between the bonding pads 13. If the distance between the bonding pads 13 is less than or equal to the distance between the bonding pads 13, even if the dummy wiring 11 is peeled off due to dicing or the like and becomes a conductive dust, the cause of the occurrence of defects can be prevented without shorting between the bonding pads 13. It can be lost. Further, the width a of the dummy wiring 11 is, for example, 30 μm or less, 20 μm or less is frequently used, preferably 10 μm or less, and the distance between the bonding pads 13 can be, for example, about 10 μm. Even if the dummy wiring 11 having a size is formed, the parasitic capacitance of the wiring 10 does not increase, and a problem of delaying a signal transmitted to the wiring 10 does not occur. As a result, the performance of the logic integrated circuit device is not degraded.

  The length b of the dummy wiring 11 is at least twice the minimum line width, and the distance between the bonding pads 13 is, for example, 10 μm or less in the scribe region. By setting the length b of the dummy wiring 11 to be larger than the width a and not more than twice the minimum line width, when both the width and length of the dummy wiring 11 are the minimum line width, the dummy wiring 11 However, by setting the length b to at least twice the minimum line width, the dummy wiring 11 can be reliably resolved even if the width a is the minimum line width. The processing can be ensured. The distance b between the bonding pads 13 is, for example, 10 μm or less for the same reason as in the case of the width a.

  Further, the length b of the dummy wiring 11 is, for example, 30 μm or less like the width a, 20 μm or less is frequently used, and preferably 10 μm or less.

  In the first embodiment, the dummy wiring 11 has a rectangular shape, but may be a triangle, a trapezoid, a circle, or another polygon as long as the above condition is satisfied. Further, in order to minimize the parasitic capacitance of the wiring 10, it is preferable that the dummy wiring 11 has a shape as small as possible, and the number thereof is preferably as small as possible. Therefore, in order to minimize the parasitic capacitance of the wiring 10 within the range satisfying the above conditions, the member interval S is set to twice the wiring height H, the dummy wiring width a is set to the minimum line width, and the dummy wiring Most preferably, the length b is twice (or more) the minimum line width. In the present embodiment, for example, the width a is 0.6 to 1 μm and the length b is 10 to 20 μm.

  The wiring 10 and the dummy wiring 11 are covered with an insulating film 12. The surface of the insulating film 12 is polished by the CMP method, and the surface is completely flattened.

  4 is an enlarged cross-sectional view showing a wiring portion in FIG.

  The insulating film 12 is a laminated film of an insulating film 12a, an insulating film 12b, an insulating film 12c, and an insulating film 12d from the side in contact with the wiring 10 and the dummy wiring 11.

  The insulating film 12a can be a silicon oxide film formed by, for example, a CVD method using TEOS. As shown in the drawing, the insulating film 12a is formed with a surface shape faithful to the step. The film thickness can be, for example, 300 nm.

  The insulating film 12b can be, for example, an inorganic SOG film, a silicon oxide film or a polysilazane film formed by a high-density plasma CVD method, and a film having a property of filling a recess can be used. Therefore, as shown in the drawing, the film is embedded in the recess and the film thickness of the protrusion is reduced. The reason why the recesses can be filled with the insulating film 12b is that the dummy wiring 11 is formed under the above-described conditions, and the interval between the recesses formed by the dummy wiring 11 fills the insulating film 12b. This is because the interval is less than or equal to the necessary interval. The film thickness can be, for example, 125 nm at the convex portion.

  The insulating film 12c can be, for example, a silicon oxide film formed by a CVD method using TEOS, and its surface is polished by the CMP method. Since the dummy wiring 11 is formed on this polished surface, a completely flat surface is realized. The film thickness can be, for example, 500 nm at the convex portion.

  The insulating film 12d can be a silicon oxide film formed by, for example, a CVD method using TEOS. The film thickness can be, for example, 200 nm. The insulating film 12d can be omitted. In this case, when the insulating film 12c is deposited, it is necessary to add it by the thickness of the insulating film 12d.

  In the upper layer of the insulating film 12, the wiring 14, dummy wiring 15 and insulating film 16 of the second wiring layer are formed. Furthermore, the wiring 17, dummy wiring 18 and insulating film 19 of the third wiring layer, and wiring of the fourth wiring layer 20, a dummy wiring 21 and an insulating film 22 are formed. The wiring layers and insulating films of the wirings 14, 17, 20, the dummy wirings 15, 18, 21 and the insulating films 16, 19, 22 are the same as the wiring 10, the dummy wiring 11, and the insulating film 12 of the first wiring layer. It is configured.

  Further, the wiring 23 and the insulating film 24 of the fifth wiring layer are formed as an upper layer of the fourth wiring layer, and the passivation film 25 is formed. The passivation film 25 can be a silicon nitride film, for example. The wiring 23 includes a bonding pad 13.

  Next, a method for manufacturing the logic integrated circuit device according to the first embodiment will be described with reference to FIGS.

  5 to 11 are sectional views showing an example of the manufacturing method of the logic integrated circuit device according to the first embodiment in the order of steps.

  First, as shown in FIG. 5, a semiconductor substrate 1 is prepared, and a shallow groove 2 is formed using photolithography and etching techniques. Thereafter, a silicon oxide film is deposited on the main surface of the semiconductor substrate 1 including the shallow groove 2, and the silicon oxide film is polished using a CMP method or the like to form the element isolation region 3. Thereafter, n-type and p-type well regions may be formed.

  Next, as shown in FIG. 6, a silicon oxide film to be the gate insulating film 5 is formed by thermal oxidation or thermal CVD, and a polycrystalline silicon film is further deposited by CVD. The polycrystalline silicon film is patterned using photolithography and etching techniques to form the gate wiring 6 (gate electrode 7). Thereafter, impurities are ion-implanted in a self-aligned manner with respect to the gate electrode 7 using the gate electrode 7 as a mask to form an impurity semiconductor region 8. Further, after depositing a silicon oxide film, anisotropic etching is performed to form sidewall spacers 8b. Thereafter, the impurity semiconductor region 8 may have a so-called LDD structure by ion implantation of a higher concentration of impurities.

  Next, as shown in FIG. 7, a PSG film is formed and planarized by using an etch back method or a CMP method, and an interlayer insulating film 9 is formed. Thereafter, an aluminum film is deposited by sputtering or vapor deposition. Further, the aluminum film is patterned using photolithography and etching techniques to form the wiring 10 and the dummy wiring 11. The patterning is performed according to the conditions of the dummy wiring 11 described above.

  Next, as shown in FIG. 8, an insulating film 12a is formed by a CVD method using TEOS. As the CVD method, for example, a plasma CVD method can be used, but a thermal CVD method using ozone together may be used. The thickness of the insulating film 12a is 300 nm. 8 to 11 are sectional views showing only the wiring layer, and the lower layer thereof is omitted.

  Thereafter, an insulating film 12b is formed using an inorganic SOG film, or an organic SOG film is applied and then etched back to fill a gap formed by the wiring 10 and the dummy wiring 11. The inorganic SOG film can be formed by applying inorganic SOG and baking it. The film thickness of the insulating film 12b is 125 nm at the convex portion. The insulating film 12b may be a silicon oxide film or a polysilazane film formed by a high density plasma CVD method.

  When the gap is filled with the insulating film 12b, since the dummy wiring 11 is formed, the width of the gap is small, and the gap can be satisfactorily filled with the insulating film 12b. That is, the thickness of the concave portion can be made thicker than that of the convex portion. As a result, the unevenness of the surface of the insulating film 12b is relaxed, and the height difference can be small.

  Next, as shown in FIG. 9, an insulating film 12c is formed by a CVD method using TEOS. The film thickness of the insulating film 12c can be 700 nm. For example, in the case of FIG. 29 in which the dummy wiring 11 is not provided, the insulating film 12c needs to have a film thickness of about 1700 nm. However, since the dummy wiring 11 is provided in the first embodiment, the film thickness is increased. It can be as thin as 700 nm. As a result, the deposition process of the insulating film 12c can be shortened and the process load can be reduced.

  Next, as shown in FIG. 10, the surface of the insulating film 12c is polished and planarized by the CMP method. In the first embodiment, the surface shape of the insulating film 12c reflects the shapes of the wiring 10 and the dummy wiring 11 and further the shape of the insulating film 12b, and therefore has a substantially uniform height regardless of the location. As a result, the polishing rate becomes almost uniform regardless of the location, and the surface of the insulating film 12c can be almost completely planarized. Further, since the thickness of the insulating film 12c is as thin as 700 nm, the amount of CMP polishing can be reduced, and the process load of the CMP polishing process can be reduced. The polishing amount can be 200 nm.

  Next, surface cleaning after CMP polishing is performed, and as shown in FIG. 11, an insulating film 12d is formed by a CVD method using TEOS. The film thickness of the insulating film 12d can be 200 nm. Note that the insulating film 12d may be omitted, and the thickness of the insulating film 12c may be set to 900 nm.

  In this way, the first wiring layer is completed. Thereafter, the second to fourth wiring layers can be formed in the same manner as the first wiring layer, and the fifth wiring layer can be formed in the same manner. Thereafter, a passivation film 25 is formed to almost complete the logic integrated circuit device shown in FIG.

  According to the manufacturing method of the first embodiment, the surfaces of the insulating films 12, 16, 19, and 22 are completely planarized, and the deposition process of the CMP film and the CMP polishing process are shortened. The process load can be reduced. Such an effect is particularly noticeable when the wiring is generally a multilayer wiring of three or more layers, such as a logic element.

  In the first embodiment, the case where the number of wiring layers is five has been exemplified. However, the present invention may be applied to more or fewer layers, and the number of wiring layers is arbitrary.

(Embodiment 2)
FIG. 12 is a cross-sectional view showing an example of a logic integrated circuit device according to another embodiment of the present invention.

  The logic integrated circuit device according to the second embodiment is almost the same as the logic integrated circuit device described in the first embodiment except for the fifth wiring layer. Therefore, in the following description, description of the same part is abbreviate | omitted and only a different part is demonstrated.

  The logic integrated circuit device according to the second embodiment has a dummy wiring 26 in addition to the wiring 23 in the fifth wiring layer. The conditions for arranging the dummy wiring 26 are substantially the same as the conditions for the dummy wiring 11 described in the first embodiment. However, since the bonding pad 13 is included in the wiring 23 of the fifth wiring layer, the arrangement conditions of the dummy wiring 26 are different around the bonding pad 13.

  FIG. 13 is a plan view showing the arrangement of the wirings 23 and the dummy wirings 26 in the fifth wiring layer. In the periphery of the bonding pad 13, a forbidden area 27 in which the dummy wiring 26 is not disposed is provided. The forbidden region 27 can be in a range of 20 μm from the end of the bonding pad 13.

  According to such a logic integrated circuit device, since the dummy wiring 26 is also formed in the fifth wiring layer, the surface of the passivation film 25 can be completely planarized. As a result, the BLM (Ball Limiting Metalization) film 29 serving as the base film of the bump 28 can be precisely processed as shown in FIG. Further, by providing the prohibition area 27 around the bonding pad 13, it is possible to reliably perform automatic detection of the bonding pad 13 by the wire bonding apparatus.

  In the second embodiment and the first embodiment described above, the dummy wirings 11, 15, 18, 21, and 26 can also be formed in the scribe area A, but in the scribe area A or other areas, When the photolithography markers 30a and 30b as shown in FIGS. 15A and 15B are formed, the dummy wirings 11, 15, 18, 21, and 26 are prohibited from being arranged around the markers 30a and 30b. Regions 31a and 31b can be provided. The prohibited areas 31a and 31b can be in a range of 60 μm from the ends of the markers 30a and 30b.

  By providing such prohibited areas 31a and 31b, it is possible to satisfactorily automatically detect the markers 30a and 30b in the exposure apparatus used for photolithography.

  The forbidden areas 31a and 31b are applied only to the dummy wiring 26 constituted by at least the uppermost wiring layer, and may not be applied to the dummy wirings 11, 15, and 18 which are lower wirings. The wiring itself may not be provided.

(Embodiment 3)
FIG. 16 is a cross-sectional view showing an example of a DRAM according to another embodiment of the present invention.

  The semiconductor substrate 1, shallow groove 2, element isolation region 3 and active region 4 of the DRAM of the third embodiment are the same as those of the first embodiment. A p-type well region 32 and an n-type well region 33 are formed on the main surface of the semiconductor substrate 1.

  In the active region 4 of the p-type well region 32, a selection MISFET Qt constituting a memory cell M of the DRAM and a MISFET Qn of a peripheral circuit are formed. In the active region 4 of the n-type well region 33, a MISFET Qp of a peripheral circuit is formed. Yes.

  In FIG. 16, the left side is a memory cell formation region, and the central part and the right side are peripheral circuit formation regions. The memory cell M of the DRAM has a selection MISFET Qt and a storage capacitor SN that is a capacitor.

  The gate electrode 7 of the MISFET Qt, Qn, Qp is made of, for example, a polycrystalline silicon film, and a silicide layer 7a is formed on the surface thereof. Impurity semiconductor regions 8 are formed in the active region 4 on both sides of the gate electrode 7 of the MISFETs Qt, Qn, Qp, and constitute source / drain regions of the MISFET. The conductivity type of the impurity semiconductor region 8 differs depending on the conductivity type of the MISFET. The MISFETs Qt and Qn are n-type and the MISFET Qp is p-type. Although the impurity semiconductor region 8 is illustrated as having an LDD structure with respect to the MISFETs Qn and Qp of the peripheral circuit, the impurity semiconductor region 8 may not be an LDD.

  A gate wiring 6 and a dummy gate wiring (dummy member) 34 are formed in the same layer of the gate electrode 7. The gate electrode 7 is also a part of the gate wiring 6. Since the gate wiring 6 and the dummy gate wiring 34 are formed at the same time (in the same layer) as the gate electrode 7, silicide layers 6a and 34a are formed on the surfaces thereof. Sidewall spacers 8b and cap insulating films 8c made of a silicon oxide film are formed on the side and upper surfaces of the gate wiring 6 and the dummy gate wiring 34, respectively, and an insulating film 35 is formed thereon. The insulating film 35 can be a TEOS silicon oxide film, for example. Over the insulating film 35, an insulating film 36 flattened by the CMP method is formed. The insulating film 36 can be a BPSG film, for example. In the third embodiment, since the dummy gate wiring 34 is provided, the insulating film 36 can be planarized almost completely. Since complete flattening can be achieved in this way, it is possible to mass-produce products having a fine pattern of 0.2 μm level even when the focal depth of lithography is shallow as shown in FIG.

  The arrangement of the dummy gate wiring 34 follows the same conditions as the conditions of the dummy wiring 11 described in the first embodiment. The dummy gate wiring 34 is not arranged in the region where the connection hole is formed. Thereby, opening of a connection hole can be performed without a problem. Further, the dummy gate wiring 34 is mainly formed on the element isolation region 3.

  An insulating film 37 made of, for example, a TEOS silicon oxide film can be formed on the insulating film 36, but may be omitted.

  Over the insulating film 37, a DRAM bit line 38, a wiring 39 and a dummy wiring 40 formed in the same layer are formed. These wirings can be a polycrystalline silicon film having, for example, a CVD tungsten film as an adhesive layer. The dummy wiring 40 follows the same conditions as the conditions of the dummy wiring 11 described in the first embodiment. However, it is not arranged in the region where the connection hole is formed. Thereby, opening of a connection hole can be performed without a problem. In addition, sidewall spacers 41b and cap insulating films 41c made of a silicon oxide film are formed on the side surfaces and upper surfaces of the bit lines 38, the wirings 39, and the dummy wirings 40, respectively, and an insulating film 42 is formed thereon. The insulating film 42 can be a BPSG film, for example, and is polished and planarized by a CMP method. An insulating film 43 made of, for example, a TEOS silicon oxide film can be formed on the insulating film 42, but can be omitted. In the third embodiment, since the dummy wiring 40 is provided, the insulating film 42 can be planarized almost completely.

  Over the insulating film 43, the storage capacitor SN of the DRAM and the first metal wiring layer are formed. The storage capacitor SN includes a lower electrode 45 connected to the impurity semiconductor region 8 of the MISFET Qt through a plug 44, and a plate electrode 47 formed to face the lower electrode 45 through a capacitor insulating film 46. . The storage capacitor SN is covered with an insulating film 48. Further, the storage capacitor SN is covered with an insulating film 49 made of, for example, a silicon oxide film formed by a high density plasma method, and a first layer wiring 50 and a dummy wiring 51 are formed on the insulating film 49. The wiring 50 is connected to the plate electrode 47 or the impurity semiconductor region 8 on the main surface of the semiconductor substrate 1 through a connection hole. The wiring 50 and the dummy wiring 51 are formed at the same time, and can be, for example, a tungsten film or an aluminum film with CVD tungsten as an adhesive layer. The dummy wiring 51 is arranged under the same conditions as the dummy wiring 11 described in the first embodiment. However, it is not arranged in the memory mat area where the storage capacitor SN is formed.

  The wiring 50 and the dummy wiring 51 are covered with an insulating film 52 made of, for example, a silicon oxide film or a polysilazane film by a high-density plasma CVD method, and an insulating film 53 made of, for example, a TEOS silicon oxide film is formed. The insulating film 53 is polished and planarized by the CMP method. The flatness of the insulating film 53 can be almost completely flat because the dummy wiring 51 is formed.

  On the insulating film 53, a second layer wiring 54, a dummy wiring 55 and an insulating film 56, and a third layer wiring 57, a dummy wiring 58 and an insulating film 59 are formed. The wiring 54, the dummy wiring 55, the insulating film 56, the wiring 57, the dummy wiring 58, and the insulating film 59 can be the same as the wiring 10, the dummy wiring 11, and the insulating film 12 in the first embodiment.

  According to the DRAM of the third embodiment, dummy members 34, 40, 51 are provided in the gate wiring 6, the bit line 38, the first layer wiring 50, the second layer wiring 54, and the third layer wiring 57. , 55 and 58, the flatness of the insulating film of each layer can be made perfect. Further, by disposing the dummy gate wiring 34 and the dummy wirings 40, 51, 55, 58 between the memory cell formation region and the peripheral circuit region, the insulating film of each layer can be planarized.

  Next, a method for manufacturing the DRAM of the third embodiment will be described with reference to FIGS. 18 to 21 are cross-sectional views showing an example of the DRAM manufacturing method according to the third embodiment in the order of steps.

  Since the process up to the formation of the element isolation region 3 on the main surface of the semiconductor substrate 1 is the same as that of the first embodiment, a description thereof will be omitted.

  Next, as shown in FIG. 18, a silicon oxide film to be the gate insulating film 5 is formed, a polycrystalline silicon film to be the gate wiring 6, the gate electrode 7, and the dummy gate wiring 34 is deposited. After depositing the silicon oxide film to be 8c, these laminated films are patterned to form the gate wiring 6, the gate electrode 7, and the dummy gate wiring 34. The gate wiring 6 (gate electrode 7) is patterned in accordance with a normal layout rule, and the dummy gate wiring 34 substantially satisfies the conditions of the dummy wiring 11 described in the first embodiment in addition to the normal layout rule. Patterning is performed so as to be disposed on the separation region 3.

  Next, as shown in FIG. 19, sidewall spacers 8b are formed, an insulating film 35 is deposited, and then a BPSG film is deposited. Thereafter, the insulating film 36 is formed by polishing the BPSG film by a CMP method. The thickness of the BPSG film can be 800 nm, and the CMP polishing amount can be 400 nm. This is because when the dummy gate wiring 34 is not formed, it is necessary to deposit a thicker BPSG film and the amount of CMP polishing is increased, whereas the film thickness of the BPSG film is reduced and the amount of CMP polishing is reduced. This has the effect that the process load can be reduced. In addition to the BPSG film, a PSG film or a silicon oxide film formed by a high density plasma CVD method can be used.

  The sidewall spacer 8b and the cap insulating film 8c can be silicon nitride films. When a silicon nitride film is used, it is possible to perform self-alignment etching when opening the connection hole.

  Next, as shown in FIG. 20, after cleaning after CMP, an insulating film 37 is deposited to a thickness of 100 nm. The insulating film 37 can be omitted. Thereafter, after the plug 44 connected to the bit line 38 and the lower electrode 45 of the storage capacitor SN is formed, the bit line 38, the wiring 39 and the dummy wiring 40 are formed. The dummy wiring 40 is arranged under the same conditions as those of the dummy wiring 11 of the first embodiment. Further, after forming the sidewall spacer 41b and the cap insulating film 41c, a BPSG film is deposited, and the BPSG film is polished by a CMP method to form the insulating film. In addition to the BPSG film, a PSG film or a silicon oxide film formed by a high density plasma CVD method can be used. Here, since the dummy wiring 40 is formed, the surface of the insulating film 42 can be completely flattened, and at the same time, the thickness of the BPSG film can be reduced and the amount of CMP polishing can be reduced. Further, cleaning after CMP is performed, and an insulating film 43 is deposited by TEOS plasma CVD or the like. The insulating film 43 can be omitted.

  Next, as shown in FIG. 21, a storage capacitor SN is formed, a BPSG film is deposited, and a baking process is performed to form an insulating film 49. The thickness of the insulating film 49 can be 500 nm. Further, after opening the connection holes, a tungsten film to be a first layer wiring is formed by a CVD method, and an aluminum film is formed by a sputtering method. Thereafter, the aluminum film and the tungsten film are patterned to form the wiring 50 and the dummy wiring 51. The arrangement of the dummy wirings 51 is the same as the conditions of the dummy wirings 11 of the first embodiment, but is further weighted by the condition that they are not arranged in the memory mat area where the storage capacitor SN is arranged. FIG. 22 is a plan view showing this situation. Further, after depositing a BPSG film to form the insulating film 52, for example, a TEOS silicon oxide film is deposited and polished by CMP to form an insulating film 53. In addition to the BPSG film, a PSG film or a silicon oxide film formed by a high density plasma CVD method can be used. Here, since the dummy wiring 51 is formed, the surface of the insulating film 53 can be completely flattened, and at the same time, the thickness of the TEOS silicon oxide film can be reduced and the amount of CMP polishing can be reduced.

  Thereafter, the second-layer wiring layer and the third-layer wiring layer are formed as in the first embodiment, and the DRAM of the third embodiment is almost completed.

  According to the manufacturing method of the third embodiment, the process load can be reduced at the same time that the insulating film of each layer is completely planarized.

  Also in the third embodiment, as shown in the first and second embodiments, the dummy member can be formed in the scribe region, and the dummy member is not disposed around the bonding pad and the marker. be able to.

  It is also possible not to arrange dummy members around the area where the fuse is formed.

  Of course, the dummy gate wiring 34 as in the third embodiment may be provided in the semiconductor integrated circuit device shown in the first and second embodiments.

(Embodiment 4)
FIG. 23 is a cross-sectional view showing an example of a semiconductor integrated circuit device according to another embodiment of the present invention.

  In the semiconductor integrated circuit device of the present invention, dummy regions 60 are formed in the element isolation regions D and 3 that define the active region 4 of the semiconductor substrate 1. That is, the dummy region (dummy member) 60 is formed in the wide element isolation region D. Since elements, wirings, and the like on the semiconductor substrate other than the element isolation structure are the same as those in the first embodiment, description thereof is omitted. The dummy region 60 may be formed also in the scribe region, and is arranged under conditions similar to the conditions of the dummy wiring 11 of the first embodiment. Since the dummy region 60 is formed in this way, when the element isolation regions D and 3 are formed using the CMP method, dishing does not occur in the element isolation regions D and 3, and the surface of the semiconductor substrate 1 is planarized. It becomes possible to do. In addition, by optimizing the number of dummy regions 60 which are small, it is possible to prevent an increase in parasitic capacitance due to the dummy regions 60 and maintain the performance of the semiconductor integrated circuit device.

  In addition, it is better not to arrange the dummy region 60 in the region where the gate wiring 6 is formed on the main surface of the semiconductor substrate 1. That is, a forbidden region 70 in which the dummy region 60 is not disposed is provided below the gate wiring 6. The situation is shown in FIG. 24 and FIG. Since the dummy region 60 has the same function as that of the active region 4 of the semiconductor substrate 1, if the gate wiring 6 is formed immediately above the dummy region 60, the gate wiring 6 faces the active region 4 through the gate insulating film 5. Although the parasitic capacitance of the gate wiring 6 increases, the parasitic capacitance of the gate wiring 6 does not increase when the dummy region 60 is not disposed in the region where the gate wiring 6 is formed. As a result, the performance of the semiconductor integrated circuit device is not degraded.

  In the present embodiment, the dummy region 60 is formed of a square having a width a and a length b of about 15 to 20 μm, for example, but is not limited to this and may be a rectangle or other shapes.

  Next, a method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment will be described with reference to FIGS.

  First, as shown in FIG. 25, a silicon nitride film 61 is deposited on the main surface of the semiconductor substrate 1, and the silicon nitride film 61 and the semiconductor substrate 1 are patterned to form shallow grooves 2. The shallow groove 2 includes both the element isolation region 3 and the dummy region 60. That is, the shallow groove 2 is formed so that the dummy region 60 is formed in the element isolation regions D and 3 that define the active region 4.

  Next, as shown in FIG. 26, for example, a silicon oxide film is deposited by the CVD method, the silicon oxide film is polished by the CMP method as the primary polishing, and the silicon oxide film is buried in the shallow groove 2, thereby isolating the element isolation region. D and 3 and dummy region 60 are formed. For the primary polishing, an alkaline slurry using silicon oxide particles as an abrasive can be used. In this case, since the polishing rate ratio between the silicon oxide film and the silicon nitride film is 3 to 4 to 1, the thickness of the silicon nitride film needs to be increased to some extent.

  Next, as shown in FIG. 27, further secondary polishing can be performed to remove foreign substances and damaged layers. The secondary polishing can be performed using a soft pad, and a chemical solution may be used, or pure water may be used. Thereafter, both surfaces of the semiconductor substrate 1 are scrubbed and washed with hydrofluoric acid, and further washed with ammonia and hydrochloric acid, and then the element isolation region 3 and the dummy region 60 are etched back. The etch back can be performed by dry etching or wet etching. By performing the etch back of the element isolation region 3 and the dummy region 60 in this way, the height of the element isolation region 3 and the dummy region 60 can be made equal to or lower than the height of the active region 4. . This makes it possible to process fine gate wiring. This etch back process can be omitted.

  Finally, the silicon nitride film 61 is removed to prepare the semiconductor substrate 1 on which the element isolation regions D and 3 defining the active region 4 shown in FIG. 28 are formed. Since the subsequent steps are the same as those in the first embodiment, a description thereof will be omitted.

  The primary polishing can be performed using a slurry using cerium oxide as an abrasive. In this case, the polishing rate ratio between the silicon oxide film and the silicon nitride film is 30 to 50: 1, and the thickness of the silicon nitride film 61 can be 50 nm or less. Since such a film thickness can be ignored in the process design, it is possible to omit the etch back of the element isolation region 3 and the dummy region 60 described above. As a result, the process can be simplified.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fourth embodiments, the CMP process is used as the insulating film polishing process. However, if the present invention is used, a certain degree of flatness can be secured before the CMP polishing. It is also possible to use it. In this case, the finishing step is not limited to the CMP method, and dry belt polishing or lapping method can be used.

  Further, as shown in FIG. 32, in the fourth embodiment, the dummy gate wiring 34 shown in the third embodiment may be provided. 33 is a plan view of the main part of FIG. The dummy gate wiring 34 is configured to extend over the element isolation regions D and 3 and the dummy region 60. The dummy gate wiring 34 is configured in an electrically floating state, and is formed on the dummy region 60 via the gate insulating film 5.

  When the semiconductor region 8 that is the source / drain region of the MISFET Q1 is formed, the semiconductor region 8 is not formed in the dummy region 60 by ion implantation using the resist film covering the element isolation regions D and 3 as a mask.

  Further, as shown in FIG. 34, the dummy gate wiring 34 may be formed long in a wiring shape. Thereby, the flatness of the surface of the insulating film 9 can be improved.

  In the third embodiment, it is needless to say that the dummy region 60 shown in the fourth embodiment may be provided.

1 Semiconductor substrate
2 shallow groove
D, 3 element isolation region
4 Active region
5 Gate insulation film
6 Gate wiring
6a Silicide layer
7 Gate electrode
7a Silicide layer
8 Impurity semiconductor region
8b Side wall spacer
8c Cap insulating film
9 Interlayer insulating film 10, 14, 17, 20, 23 Wiring 11, 15, 18, 21, 26 Dummy wiring 12, 12a to d Insulating film
13 Bonding pad 16, 19, 22, 24 Insulating film
25 Passivation film
27 Prohibited areas
28 Bump
29 BLM film 30a, 30b Marker 31a, 31b Prohibited area
32 p-type well region
33 n-type well region
34 Dummy gate wiring 35-37 Insulating film
38 Bit lines 39, 50, 54, 57 Wiring 40, 51, 55, 58, 60 Dummy wiring
41b Side wall spacer
41c Cap insulating film 42, 43, 48, 49, 52, 53, 56, 59 Insulating film
44 plug
45 Lower electrode
46 Capacitive insulation film
47 Plate electrode
61 Silicon nitride film
101 Interlayer insulation film
102 Wiring
103 1st insulating film
104 Second insulating film
105 Third insulating film
A scribe area
B pad / peripheral circuit area
C Logic circuit area
Qt selection MISFET
Qn MISFET
Qp MISFET
Q1 MISFET
S Member spacing
SN storage capacity
a width
b Length

Claims (5)

A semiconductor substrate;
An active region formed on the semiconductor substrate and functioning as a part of a MISFET;
A gate electrode formed on the active region and functioning as a part of the MISFET;
A plurality of dummy regions formed on the semiconductor substrate and not functioning as part of the MISFET;
A groove defining the active region and the plurality of dummy regions;
An insulating film embedded in the groove;
Have
On the semiconductor substrate, a plurality of dummy gate wirings that do not function as a part of the MISFET and are in the same layer as the gate electrode are formed,
The plurality of dummy regions are each formed in the same shape and are periodically arranged,
The plurality of dummy gate wirings are each formed in the same shape and are periodically arranged,
Each of the plurality of dummy gate wiring least one dummy area on one of both before Symbol plurality of dummy regions, and are formed so as to extend on the insulating film,
A semiconductor integrated circuit device, wherein an interlayer insulating film is formed on the active region, the gate electrode, the plurality of dummy regions, and the plurality of dummy gate wirings. A semiconductor substrate;
An active region formed on the semiconductor substrate and functioning as a part of a MISFET;
A gate electrode formed on the active region and functioning as a part of the MISFET;
A plurality of dummy regions formed on the semiconductor substrate and not functioning as part of the MISFET;
A groove defining the active region and the plurality of dummy regions;
An insulating film embedded in the groove;
Have
On the semiconductor substrate, a plurality of dummy gate wirings that do not function as a part of the MISFET and are in the same layer as the gate electrode are formed,
The plurality of dummy regions are each formed in the same shape and arranged at the same pitch,
The plurality of dummy gate lines are formed in the same shape, and are arranged at the same pitch,
Each of the plurality of dummy gate wiring least one dummy area on one of both before Symbol plurality of dummy regions, and are formed so as to extend on the insulating film,
A semiconductor integrated circuit device, wherein an interlayer insulating film is formed on the active region, the gate electrode, the plurality of dummy regions, and the plurality of dummy gate wirings. The semiconductor integrated circuit device according to claim 1, wherein:
The semiconductor integrated circuit device, wherein the plurality of dummy regions and the plurality of dummy gate wirings are formed in a scribe region. The semiconductor integrated circuit device according to any one of claims 1 to 3,
Each of the plurality of dummy gate wirings is in a floating state. The semiconductor integrated circuit device according to any one of claims 1 to 4,
Each of the plurality of dummy gate lines has a rectangular shape.

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