GB9625363D0 - Method for planarizing the surface of a wafer - Google Patents

Method for planarizing the surface of a wafer

Info

Publication number
GB9625363D0
GB9625363D0 GBGB9625363.8A GB9625363A GB9625363D0 GB 9625363 D0 GB9625363 D0 GB 9625363D0 GB 9625363 A GB9625363 A GB 9625363A GB 9625363 D0 GB9625363 D0 GB 9625363D0
Authority
GB
United Kingdom
Prior art keywords
planarizing
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9625363.8A
Other versions
GB2308229A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9625363D0 publication Critical patent/GB9625363D0/en
Publication of GB2308229A publication Critical patent/GB2308229A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
GB9625363A 1995-12-16 1996-12-05 Method for planarizing the surface of a wafer Withdrawn GB2308229A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050997A KR100214073B1 (en) 1995-12-16 1995-12-16 Bpsg film forming method

Publications (2)

Publication Number Publication Date
GB9625363D0 true GB9625363D0 (en) 1997-01-22
GB2308229A GB2308229A (en) 1997-06-18

Family

ID=19440781

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9625363A Withdrawn GB2308229A (en) 1995-12-16 1996-12-05 Method for planarizing the surface of a wafer

Country Status (6)

Country Link
JP (1) JP2859864B2 (en)
KR (1) KR100214073B1 (en)
CN (1) CN1159489A (en)
DE (1) DE19651778A1 (en)
GB (1) GB2308229A (en)
TW (1) TW308714B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2994616B2 (en) * 1998-02-12 1999-12-27 キヤノン販売株式会社 Underlayer surface modification method and semiconductor device manufacturing method
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
US6051849A (en) 1998-02-27 2000-04-18 North Carolina State University Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
US6265289B1 (en) 1998-06-10 2001-07-24 North Carolina State University Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby
US6255198B1 (en) 1998-11-24 2001-07-03 North Carolina State University Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby
US6177688B1 (en) 1998-11-24 2001-01-23 North Carolina State University Pendeoepitaxial gallium nitride semiconductor layers on silcon carbide substrates
US6521514B1 (en) 1999-11-17 2003-02-18 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
US6380108B1 (en) 1999-12-21 2002-04-30 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby
US6403451B1 (en) 2000-02-09 2002-06-11 Noerh Carolina State University Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts
US6261929B1 (en) 2000-02-24 2001-07-17 North Carolina State University Methods of forming a plurality of semiconductor layers using spaced trench arrays
KR20120098095A (en) * 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 Method for manufacturing semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2538722B2 (en) * 1991-06-20 1996-10-02 株式会社半導体プロセス研究所 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
TW308714B (en) 1997-06-21
CN1159489A (en) 1997-09-17
DE19651778A1 (en) 1997-06-19
JPH09181071A (en) 1997-07-11
KR100214073B1 (en) 1999-08-02
KR970052884A (en) 1997-07-29
GB2308229A (en) 1997-06-18
JP2859864B2 (en) 1999-02-24

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)