KR970053627A - 수지 밀봉형 반도체 장치 - Google Patents

수지 밀봉형 반도체 장치 Download PDF

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Publication number
KR970053627A
KR970053627A KR1019960069232A KR19960069232A KR970053627A KR 970053627 A KR970053627 A KR 970053627A KR 1019960069232 A KR1019960069232 A KR 1019960069232A KR 19960069232 A KR19960069232 A KR 19960069232A KR 970053627 A KR970053627 A KR 970053627A
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South Korea
Prior art keywords
chip
island region
resin
semiconductor device
sealed semiconductor
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KR1019960069232A
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English (en)
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KR100257912B1 (ko
Inventor
도모히로 후지사키
도시카즈 세이
다께히또 이나바
Original Assignee
니시무로 타이조
가부시기가이샤 도시바
가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
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Publication of KR970053627A publication Critical patent/KR970053627A/ko
Application granted granted Critical
Publication of KR100257912B1 publication Critical patent/KR100257912B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

아일랜드 영역(6)과 복수의 내부 리드(2B,2C,2D,2E)로 형성되는 리드 프레임(1B,1C,1D,1E)과, 상기 내부 리드2B,2C,2D,2E)의 선단은 칩(5)의 평면에 수직하게 보이는 캐비티(9B,9C,9D,9E)내에 위치하며, (b)복수의 전극을 가지며 상기 리드 프레임(1B,1C,1D,1E)의 상기 아일랜드 영역(6)상에 장착된 칩(5)과, (c)상기 칩(5)의 상기 전극을 상기 내부 리드(2B,2C,2D,2E)에 연결하는 와이어를 포함하는, 수지 밀봉형 반도체 장치에 있어서, 상기 캐비티(9B,9C,9D,9E)는 상기 칩(5)의 각 측부와 각을 형성하는 세그먼트를 갖는 둘레를 가져, 상기 칩(5)의 대각선(D1)에서 코너부에 장착된 전극에 연결될 내부 리드(L1)의 선단이 상기 칩(5)의 상기 아일랜드 영역(6)에 가장 근접하게 배치되며, 상기 대각선(D1)에 수직한 상기 칩(5)의 상기 아일랜드 영역(6)에 가장 근접하게 배치되며, 상기 대각선(D1)에 수직한 상기 칩(5)의 대각선(D2)상의 코너부에 장착된 전극중 하나에 연결될 내부 리드의 선단이 상기 칩(5)의 상기 아일랜드 영역(6)으로부터 가장 멀게 배치되는 것을 특징으로 하는 수진 밀봉형 반도체 장치를 제공하는 것이다. 본 발명은, 상부 및 하부금형에 의해 형성된 공간으로 용융수지를 주입하여 반도체 장치를 밀봉하는 단계에서, 용율수지로부터 가장 큰 힘을 받는 와이어를 짧게하는 것이 가능하다. 따라서, 상기한 단계에서, 인접 와이어 사이에서 발생하는 단락을 방지하는 것이 가능하며, 이에 의해 고수율 및 고신뢰성을 갖는 수지 밀봉형 반도체 장치를 제공하는 것이다.

Description

수지 밀봉형 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명의 제1실시예에 따라 제조된, 와이어를 통해 내부 리드에 연결된 칩이 장착된 리드 프레임을 도시한 평면도이다.

Claims (11)

  1. 아일랜드 영역(6)과 복수의 내부 리드(2B,2C,2D,2E)로 형성되는 리드 프레임(1B,1C,1D,1E)과, 복수의전극을 가지며 상기 리드 프레임(1B,1C,1D,1E)의 상기 아일랜드 영역(6)상에 장착된 칩(5)과, 상기 칩(5)의상기 전극을 상기 내부 리드(2B,2C,2D,2E)에 연결하는 와이어를 포함하며, 상기 내부 리드(2B,2C,2D,2E)의선단은 칩(5)의 평면에 수직하게 보이는 캐비티(9B,9C,9D,9E)를 형성하며, 상기 아일랜드 영역(6)이 상기캐비티(9B,9C,9D,9E) 내에 위치하는 수지 밀봉형 반도체 장치에 있어서, 상기 캐비며,(9B,9C,9D,9E)는 상기칩(5)의 각 측부와 각을 형성하는 세그먼트를 갖는 둘레를 가져, 상기 칩(5)의 코너부에 장착된 전극에 연결될 내부 리드의 선단이 내부리드의 다른 선단보다 상기 칩(5)의 상기 아일랜드 영역(6)에 가장 가깝게 배치되는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  2. 제1항에 있어서, 상기 캐비티(9B,9D,9E)는 다각형이며, 이 다각형은 5각형 이상인 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  3. 제1항에 있어서, 상기 캐비티(9B)는 8각형이며, 이 8각형의 8개의 8개의 정점은 상기 칩(5)의 연장 대각선(D1)과 상기 칩(5)의 중앙으로부터 상기 칩(5)의 측부 중점까지 연결하는 연장선 상에 위치하는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  4. 제1항에 있어서, 상기 캐비티(9B,9D,9E)는 아치형 세그먼트를 가지지 않는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  5. 제1항에 있어서, 상기 캐비티(9C)는 원형인 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  6. 아일랜드 영역(6)과 이 아일랜드 영역(6)의 둘레에 배치되는 복수의 내부 리드(2B,2C,2D,2E)로 형성되는 리드 프레임(1B,1C,1D,1E)과, 복수의 전극을 가지며 상기 리드 프레임(1B,1C,1D,1E)의 상기 아일랜드 영역(6)상에 장착된 칩(5)과, 상기 칩(5)의 상기 전극을 상기 내부 리드(2B,2C,2D,2E)에 연결하는 와이어를 포함하는 수지 밀봉형 반도체 장치에 있어서, 상기 칩(5)의 코너부에 위치하는 전극(B)에 연결될 내부 리드(A)가 상기 아일랜드 영역(6)에 근접하게 배치되어, 상기 전극(B)에 상기 내부 리드(A)를 연결하는 와이어가 다른 와이어들 보다 더 짧은 길이를 갖는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  7. 아일랜드 영역(6)과 복수의 내부 리드(2B,2C,2D,2E)로 형성되는 리드 프레임(1B,1C,1D,1E)과, 복수의 전극을 가지며 상기 리드 프레임(1B,1C,1D,1E)의 상기 아일랜드 영역(6)상에 장착된 칩(5)과, 상기 칩(5)의 상기 전극을 상기 내부 리드(2B,2C,2D,2E)에 연결하는 와이어를 포함하며, 상기 내부 리드(2B,2C,2D,2E)의 선단은 칩(5)의 평면에 수직하게 보이는 캐비티(9B,9C,9D,9E)를 형성하며, 상기 아일랜드 영역(6)이 상기 캐비티 (9B,9C,9D,9E)내에 위치하는 수지 밀봉형 반도체 장치에 있어서, 상기 캐비티(9B,9C,9D,9E)는 상기 칩(5)의 각 측부와 각을 형성하는 세그먼트를 갖는 둘레를 가져, 상기 칩(5)의 대각선(D1)에서 코너부에 장착된 전극에 연결될 내부 리드(L1)의 선단이 상기 칩(5)의 상기 아일랜드 영역(6)에 가장 근접하게 배치되며, 상기 대각선(D1)에 수직한 상기 칩(5)의 대각선(D2)상의 코너부에 장착된 전극 중 하나에 연결될 내부 리드의 선단이 상기 칩(5)의 상기 아일랜드 영역(6)으로부터 가장 멀게 배치되는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  8. 아일랜드 영역(6)과 복수의 내부 리드(2B,2C,2D,2E)로 형성되는 리드 프레임(1B,1C,1D,1E)과, 복수의 전극을 가지며 상기 리드 프레임(1B,1C,1D,1E)의 상기 아일랜드 영역(6)상에 장착된 칩(5)과, 상기 칩(5)의 상기 전극을 상기 내부 리드(2B,2C,2D,2E)에 연결하는 와이어를 포함하며, 상기 내부 리드(2B,2C,2D,2E)의 선단은 칩(5)의 평면에 수직하게 보이는 캐비티(9B,9C,9D,9E)를 형성하며, 상기 아일랜드 영역(6)이 상기 캐비티 (9B,9C,9D,9E)내에 위치하는 수지 밀봉형 반도체 장치에 있어서, 상기 캐비티(9B,9C,9D,9E)는 상기 칩(5)의 대각선(D1)상의 코너부에 장착된 전극에 내부 리드(L1)를 연결하는 와이어의 길이가 가장 짧으며, 상기 대각선(D1)에 수직한 상기 칩(5)의 대각선(D2)상의 코너부에 장착된 전극 중 하나를 연결하는 와이어의 길이가 가장 길도록 형성되는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  9. 제8항에 있어서, 상부 및 하부 금형(15,16)에 의해 형성되고 상기 칩(5)이 위치하는 공간(22A,22B)으로용융수지(18)를 도입시키는 게이트(21)에 수직하게 상기 대각선(D1)이 연장하고, 상기 대각선(D2)이 상기게이트(21)와 동일한 방향으로 연장하도록, 상기 칩(5)을 위치시키는 것을 특징으로 하는 수지 밀봉형 반도체장치.
  10. 제8항에 있어서, 상기 게이트(21)에 보다 근접하게 위치한 상기 캐비티(9E)의 절반부(H1)와 상기 게이트(21)로부터 보다 떨어져 위치한 상기 캐비티(9E)의 절반부(H1)가 서로 비대칭인 것을 특징으로 하는 수지 밀봉형 반도체 장치.
  11. 제10항에 있어서, 상기 내부 리드(L1)로부터 보다 떨어져 위치한 관련 내부 리드에 전극을 연결하는 와이어의 길이가 보다 길게 되도록, 상기 캐비티(9E)의 다른 절반부(H2)에 위치한 내부 리드(2E)가 설치되는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960069232A 1995-12-20 1996-12-20 수지 밀봉형 반도체 장치 KR100257912B1 (ko)

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