IT1317559B1 - Telaio di supporto per chip avente interconnessioni a bassa resistenza. - Google Patents

Telaio di supporto per chip avente interconnessioni a bassa resistenza.

Info

Publication number
IT1317559B1
IT1317559B1 IT2000MI001145A ITMI20001145A IT1317559B1 IT 1317559 B1 IT1317559 B1 IT 1317559B1 IT 2000MI001145 A IT2000MI001145 A IT 2000MI001145A IT MI20001145 A ITMI20001145 A IT MI20001145A IT 1317559 B1 IT1317559 B1 IT 1317559B1
Authority
IT
Italy
Prior art keywords
support frame
low resistance
chip support
leads
resistance interconnections
Prior art date
Application number
IT2000MI001145A
Other languages
English (en)
Inventor
Roberto Tiziani
Carlo Cognetti
Andrea Cigada
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000MI001145A priority Critical patent/IT1317559B1/it
Publication of ITMI20001145A0 publication Critical patent/ITMI20001145A0/it
Priority to US09/862,214 priority patent/US6838755B2/en
Publication of ITMI20001145A1 publication Critical patent/ITMI20001145A1/it
Application granted granted Critical
Publication of IT1317559B1 publication Critical patent/IT1317559B1/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
IT2000MI001145A 2000-05-23 2000-05-23 Telaio di supporto per chip avente interconnessioni a bassa resistenza. IT1317559B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000MI001145A IT1317559B1 (it) 2000-05-23 2000-05-23 Telaio di supporto per chip avente interconnessioni a bassa resistenza.
US09/862,214 US6838755B2 (en) 2000-05-23 2001-05-21 Leadframe for integrated circuit chips having low resistance connections

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000MI001145A IT1317559B1 (it) 2000-05-23 2000-05-23 Telaio di supporto per chip avente interconnessioni a bassa resistenza.

Publications (3)

Publication Number Publication Date
ITMI20001145A0 ITMI20001145A0 (it) 2000-05-23
ITMI20001145A1 ITMI20001145A1 (it) 2001-11-23
IT1317559B1 true IT1317559B1 (it) 2003-07-09

Family

ID=11445105

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000MI001145A IT1317559B1 (it) 2000-05-23 2000-05-23 Telaio di supporto per chip avente interconnessioni a bassa resistenza.

Country Status (2)

Country Link
US (1) US6838755B2 (it)
IT (1) IT1317559B1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4359110B2 (ja) * 2003-09-24 2009-11-04 三洋電機株式会社 回路装置
US6929485B1 (en) * 2004-03-16 2005-08-16 Agilent Technologies, Inc. Lead frame with interdigitated pins
US20100032183A1 (en) * 2007-03-01 2010-02-11 Brandenburg Scott D Compliant pin strip with integrated dam bar
JP4783442B2 (ja) * 2009-03-18 2011-09-28 株式会社東芝 Ｅｓｄ保護検証装置及びｅｓｄ保護検証方法
JP2018107296A (ja) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4534105A (en) * 1983-08-10 1985-08-13 Rca Corporation Method for grounding a pellet support pad in an integrated circuit device
JPH01312866A (ja) * 1988-06-10 1989-12-18 Nec Kyushu Ltd 半導体装置用リードフレーム
JPH0451553A (ja) * 1990-06-19 1992-02-20 Mitsubishi Electric Corp 半導体装置
JP3046630B2 (ja) * 1991-02-26 2000-05-29 株式会社日立製作所 半導体集積回路装置
US5168368A (en) * 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
US5420758A (en) * 1992-09-10 1995-05-30 Vlsi Technology, Inc. Integrated circuit package using a multi-layer PCB in a plastic package
JP2765542B2 (ja) * 1995-12-20 1998-06-18 日本電気株式会社 樹脂封止型半導体装置
JPH09260575A (ja) * 1996-03-22 1997-10-03 Mitsubishi Electric Corp 半導体装置及びリードフレーム
JP2859220B2 (ja) * 1996-10-08 1999-02-17 九州日本電気株式会社 リードフレームおよびそれを用いた半導体装置の製造方法
US5898213A (en) * 1997-07-07 1999-04-27 Motorola, Inc. Semiconductor package bond post configuration
US6144089A (en) * 1997-11-26 2000-11-07 Micron Technology, Inc. Inner-digitized bond fingers on bus bars of semiconductor device package
JP3144383B2 (ja) * 1998-05-21 2001-03-12 日本電気株式会社 半導体装置
US6168975B1 (en) * 1998-06-24 2001-01-02 St Assembly Test Services Pte Ltd Method of forming extended lead package
EP1028464B1 (en) * 1999-02-11 2006-07-26 STMicroelectronics S.r.l. Semiconductor device with improved interconnections between the chip and the terminals, and process for its manufacture

Also Published As

Publication number Publication date
ITMI20001145A0 (it) 2000-05-23
ITMI20001145A1 (it) 2001-11-23
US20020043701A1 (en) 2002-04-18
US6838755B2 (en) 2005-01-04

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