JPS61292928A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61292928A
JPS61292928A JP60134012A JP13401285A JPS61292928A JP S61292928 A JPS61292928 A JP S61292928A JP 60134012 A JP60134012 A JP 60134012A JP 13401285 A JP13401285 A JP 13401285A JP S61292928 A JPS61292928 A JP S61292928A
Authority
JP
Japan
Prior art keywords
lead
gold plating
tab
semiconductor chip
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60134012A
Other languages
English (en)
Inventor
Susumu Okikawa
進 沖川
Hiroshi Mikino
三木野　博
Hiromichi Suzuki
博通 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60134012A priority Critical patent/JPS61292928A/ja
Publication of JPS61292928A publication Critical patent/JPS61292928A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
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    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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  • Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置に係り、特に、ポールボンディン
グ技術に適用して有効な技術に関するものである。
〔背景技術〕
近年、半導体装置において、金ボールボンディングに用
いられる金ワイヤが高価であるため、銅（Ｃｕ）ワイヤ
でポールボンディング（以下、鋼ボールボンディングと
いう）を行なう技術が研究開発されている。
銅ボールボンディングでは、半導体チップ側のボンディ
ングについては水素（Ｈ２）＋アルゴン（Ａｒ）ガス等
の還元雰囲気中でポール形成を行なうためボンダビリテ
ィ（Ｂ　ｏｎｄａｂｉｌｉｔｙ）は問題ないが、しかし
、リード側のボンディングが、例えば、２５０〜３００
℃のような高温度で行なわれると。
それに応じて銅ワイヤ表面が酸化し、ボンダビリティが
悪くなるという問題があった。リード材として銅系材料
が使用される場合、リード表面もまたボンディングの際
の加熱により酸化され、同様にボンダビリティが悪くな
る。
前記銅ポールボンディング技術については、日経マグロ
ウヒル社発行「日経エレクトロニクス」、１９８４年６
月１１日号、ｎｏ２、ｐ７８に記載されている。
〔発明の目的〕
本発明の目的は、銅ボールボンディング技術において、
ボンダビリティを向上させると共にコストを低減させる
ことが可能な技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。
〔発明の概要〕
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。
すなわち、半導体チップをタブに銀ペーストで接着し、
各リードの封止部側の先端部のみに所定の厚さの金メッ
キ層を施し、該各リードの金メッキ層の部分と半導体チ
ップとを銅ワイヤでポールボンディングして一気的機械
的に接続したことにより、ボンダビリティの向上をはか
ると共にコストの低減をはかったものである。
以下、本発明の構成について、実施例とともに説明する
。
なお、全回において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。
〔実施例〕
第１図乃至第４図は、本発明をリードフレームを用いた
半導体装置に適用した一実施例の構成を説明するための
図であり、第１図は、その半導体装置のタブ上に半導体
チップを塔載し、銅ワイヤでボールボンディングを行な
った状態の要部の構成を示す断面図、第２図は、その半
導体装置のリードフレームの要部の構成を示す平面図、
第３図及び第４図は、第１図の１−１切断線における断
面図である。
本実施例Ｉの半導体装置は、第１図に示すように、半導
体チップ１をタブ２の上に銀ペースト３で接着し、リー
ド４のそれぞれの封止部側の先端部のみに所定の厚さの
金メッキ層５を形成し、各々リード４の金メッキ層５の
部分と半導体チップ１とを銅ワイヤ６でボールボンディ
ングすることにより電気的に接続したものである。前記
各々のリード４の金メッキ層５の部分は、タブ２を囲ん
だドーナツ状に配置されている。また、前記タブ２及び
リード４は１例えば、鋼材又は４２アロイ（Ａｌｌｏｙ
）を用いる。タブ２及びリード４の材料として銅を用い
た場合には、第３図に示すように。
銅リード４Ａの上にアニール処理又はニッケル（Ｎｉ）
等の軟質下地ｙａ７を施し、その上に金フラッシュメッ
キ法により、はぼ０．１μ曹の膜厚の薄い金メッキ層５
を形成する。前記銅リード４の上にアニール処理又は軟
質下地のニッケル（Ｎｉ）７を施す理由は、銅と金とが
合金化しないように防止するためである。また、４２７
０イを用いた場合は、第４図に示すように、４２アロイ
リード４Ｂの上に直接会フラッシュメッキ法により、は
ぼ０．１μｍの膜厚の薄い金メッキ層５を形成する。
そして、これらの形成された金メッキ層５と銅ワイヤ６
とを超音波ボンディング装置でボンディングして両者を
電気的機械的に接続する。
このように、タブ２の上に銀ペースト３で半導体チップ
１をペレット付けし、各々のリード４のタブ２を囲んだ
ドーナツ状に配置される位置の上に、金フラッシュメッ
キ法でほぼ９．１μｍの薄い金メッキ層５を形成し、こ
の金メッキ、ｌ’Ｗ５の部分と半導体チップ１とを銅ワ
イヤ６でボールボンディングして電気的に接続したこと
により、リード４側でのポールボンデングを行なう際に
、金メッキＭ５は高温度においても酸化されないので、
ボンダビリティを向上させることができる。また、半導
体チップ１を銀ペースト３でペレット付けを行なうこと
により、タブ２の上には金メッキ層５を施す必要がなく
、Ｍワイヤ６でボンディングするので、金の量を低減す
ることができる。これにより、コストを低減させること
ができる。
以上、本発明を実施例にもとずき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
はいうまでもない。
〔効果〕
以上説明したように、本願で開示した新規な技術、によ
れば、半導体チップをタブ上に銀ベーストで接着し、各
リードの封止部側の先端部のみに所定の厚さの金メッキ
層を形成し、該各リードの金メッキ層の部分と半導体チ
ップとを鋼ワイヤでボールボンディングして電気的機械
的に接続したことにより、リード側でのポールボンデン
グを行なう際に、金メッキ層は高温度においても酸化さ
れないので、ボンダビリティを向上させることができる
。また、半導体チップを銀ペーストでペレット付けを行
なうことにより、タブの上には金メッキ層を施す必要が
なく、銅ワイヤでボンディングするようにしたので、金
の量を低減することができる。これによってコストを低
減させることができる。
【図面の簡単な説明】
第１図乃至第４図は、本発明をリードフレームを用いた
半導体装置に適用した一実施例の構成を説明するための
図であり、 第１図は、その半導体装置のタブ上に半導体チップを塔
載し、銅ワイヤでポールボンデングをｒなった状態の要
部の構成を示す断面図。 第２図は、その半導体装置のリードフレームの要部の構
成を示す平面図、 第３図及び第４図は、第１図の１−１切断線における断
面図である。 図中、１・・・半導体チップ、２・・・タブ、３・・・
銀ペースト、４・・・リード、５・・・金メッキ、６・
・・銅ワイヤ、７・・・軟質下地層である。

Claims (1)

  1. 【特許請求の範囲】 １、各リードの封止部側の先端部のみに所定の厚さの金
    メッキ層を施してなり、該各リードの金メッキ層の部分
    と半導体チップとをボンデング技術によって結合された
    銅ワイヤによって電気的機械的に接続したことを特徴と
    する半導体装置。 ２、前記各リードの金メッキ層の部分は、タブを囲んだ
    ドーナツ状に配置されていることを特徴とする特許請求
    の範囲第１項記載の半導体装置。 ３、前記各リードは、銅又は４２アロイからなっている
    ことを特徴とする特許請求の範囲第１項の半導体装置。
JP60134012A 1985-06-21 1985-06-21 半導体装置 Pending JPS61292928A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60134012A JPS61292928A (ja) 1985-06-21 1985-06-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60134012A JPS61292928A (ja) 1985-06-21 1985-06-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS61292928A true JPS61292928A (ja) 1986-12-23

Family

ID=15118311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60134012A Pending JPS61292928A (ja) 1985-06-21 1985-06-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS61292928A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172130A (ja) * 1995-12-20 1997-06-30 Nec Corp 樹脂封止型半導体装置
JP2009231322A (ja) * 2008-03-19 2009-10-08 Renesas Technology Corp 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172130A (ja) * 1995-12-20 1997-06-30 Nec Corp 樹脂封止型半導体装置
JP2009231322A (ja) * 2008-03-19 2009-10-08 Renesas Technology Corp 半導体装置の製造方法

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