KR960702675A - Hf와 카르복실산 혼합물을 사용한 반도체 처리방법(method for semiconductor processing using mixtures of the and carboxylic acid) - Google Patents

Hf와 카르복실산 혼합물을 사용한 반도체 처리방법(method for semiconductor processing using mixtures of the and carboxylic acid)

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Publication number
KR960702675A
KR960702675A KR1019950704855A KR19950704855A KR960702675A KR 960702675 A KR960702675 A KR 960702675A KR 1019950704855 A KR1019950704855 A KR 1019950704855A KR 19950704855 A KR19950704855 A KR 19950704855A KR 960702675 A KR960702675 A KR 960702675A
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South Korea
Prior art keywords
carboxylic acid
semiconductor processing
etching
processing method
mixtures
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KR1019950704855A
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English (en)
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KR100332402B1 (ko
Inventor
버하버베케 스티븐
기우센스 왈다
벨리만스 마크
달스트 마크
히인스 마크
데 블랭크 알.
헨드리크스 엠.
에프. 티젯. 곽만 엘.
에이치. 에이. 그랜네만 이.
Original Assignee
요한 밴 헬리퓨테
인터유니버시테어 마이크로일렉트로니카 센트럼
이.에이취.에이. 그레니먼
어드밴스트 세미컨덕터 매티리얼스 냄로즈 베누트스캡
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Publication of KR960702675A publication Critical patent/KR960702675A/ko
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H01L21/02049—Dry cleaning only with gaseous HF
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Silicon Compounds (AREA)
  • Weting (AREA)

Abstract

산화물층, 특히 두꺼운 SiO2층을 에칭시키고, 상기 산화물층이 가스상태에서 불화수소와 하나 또는 둘이상의 카르복실산 혼합물로 에칭되는 클린닝 처리의 마지막 단계로 이루어지는 반도체 처리방법.

Description

HF와 카르복실산 혼합물을 사용한 반도체 처리방법(METHOD FOR SEM1CONDUCTOR PROCESSING USING MIXTURES OF THE ANDCARBOXYLIC ACID)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 HF/H2O 중기상태 에칭시간의 에칭깊이와의 함수관계를 도시한 도표.
제2도는 HAc/H2O 혼합물의 액체/증기 상태도표.
제3도는 HF/HAc 증기상태 에칭시간의 에칭깊이와의 함수관계를 도시한 도표.

Claims (11)

  1. 산화물층, 특히 두꺼운 SiO2층을 에칭시키고, 상기 산화물층이 가스상태에서 불화수소와 하나 또는 둘이상의 카르복실산 혼합물로 에칭되는 클린닝 처리의 마지막 단계로 이루어지는 반도체 처리방법.
  2. 제1항에 있어서, 카르복실산이 아세트산임을 특징으로 하는 반도체 처리방법.
  3. 제1항 또는 2항에 있어서, 산화물층이 웨이퍼와의 혼합물로 처리됨을 특징으로 하는 반도체 처리방법.
  4. 제1항 내지 3항 중 어느 한 항에 있어서, HF와 카르복실산의 부분압이 1Pa와 104Pa 사이임을 특징으로하는 반도체 처리방법.
  5. 제1항 내지 4항 중 어느 한 항에 있어서, 웨이퍼가 1Pa와 104Pa 사이의 부분압으로 추가됨을 특징으로하는 반도체 처리방법.
  6. 제1항 내지 4항 중 어느 한 항에 있어서, HF와 카르복실산의 부분압이 100Pa와 1000Pa 사이임을 특징으로 하는 반도체 처리방법.
  7. 제1항 내지 5항 중 어느 한 항이 있어서, HF의 부분 중기압이 300Pa이고 카르복실산의 부분 증기압이 두꺼운 SiO2층의 에칭과 클린닝 처리에서 마지막 단계 모두에서 600Pa임을 특징으로 하는 반도체 처리방법.
  8. 제1항 내지 7항 중 어느 한 항에 있어서, 에칭이 안정된 정적모드로 수행됨을 특징으로 하는 반도체 처리방법.
  9. 제1항 내지 7항 중 어느 한 항에 있어서, 에칭이 동적모드로 수행됨을 특징으로 하는 반도체 처리방법.
  10. 제1항 내지 9항 중 어느 한 항에 있어서, 에칭이 0℃와 100℃ 사이의 온도에서 수행됨을 특징으로 하는 반도체 처리방법.
  11. 제1항 내지 10항 중 어느 한 항에 있어서, 에칭이 실온에서 수행됨을 특징으로 하는 반도체 처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950704855A 1993-05-13 1994-05-10 Hf와카르복실산혼합물을사용한반도체처리방법 KR100332402B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP93870080 1993-05-13
EP93870080.4 1993-05-13
PCT/EP1994/001534 WO1994027315A1 (en) 1993-05-13 1994-05-10 Method for semiconductor processing using mixtures of hf and carboxylic acid

Publications (2)

Publication Number Publication Date
KR960702675A true KR960702675A (ko) 1996-04-27
KR100332402B1 KR100332402B1 (ko) 2002-10-25

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KR1019950704855A KR100332402B1 (ko) 1993-05-13 1994-05-10 Hf와카르복실산혼합물을사용한반도체처리방법

Country Status (7)

Country Link
EP (1) EP0698282B1 (ko)
JP (1) JP3553939B2 (ko)
KR (1) KR100332402B1 (ko)
AT (1) ATE196214T1 (ko)
DE (1) DE69425821T2 (ko)
TW (1) TW253065B (ko)
WO (1) WO1994027315A1 (ko)

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KR100332402B1 (ko) 2002-10-25
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EP0698282A1 (en) 1996-02-28
WO1994027315A1 (en) 1994-11-24
DE69425821D1 (de) 2000-10-12
JPH09509531A (ja) 1997-09-22
ATE196214T1 (de) 2000-09-15
EP0698282B1 (en) 2000-09-06
TW253065B (ko) 1995-08-01

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