KR930014829A - 에칭방법 - Google Patents
에칭방법 Download PDFInfo
- Publication number
- KR930014829A KR930014829A KR1019920024811A KR920024811A KR930014829A KR 930014829 A KR930014829 A KR 930014829A KR 1019920024811 A KR1019920024811 A KR 1019920024811A KR 920024811 A KR920024811 A KR 920024811A KR 930014829 A KR930014829 A KR 930014829A
- Authority
- KR
- South Korea
- Prior art keywords
- gas
- etching
- silicon
- hbr
- electric field
- Prior art date
Links
- 238000005530 etching Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims abstract 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract 10
- 239000010703 silicon Substances 0.000 claims abstract 10
- 230000005684 electric field Effects 0.000 claims abstract 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract 3
- 239000001301 oxygen Substances 0.000 claims abstract 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract 3
- 239000000203 mixture Substances 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
Abstract
주파수전계와 그의 전계에 직교하는 전계에 의하여 마그네트론 방전을 발생시키어 에칭가스의 플라즈마를 발생시키고 폴리 실리콘층에 대표되는 실리콘 함유층을 가지는(피처리체를 플라즈마 중에 노출하여 실리콘 함유층을 에칭할때에 에칭가스와 HBr 가스, HBr가스와 Cl2가스와 혼합 가스, 또는 HBr 가스와 Cl2가스의 혼합가스를 주체로 하는 것, 또는 여기에 O2와 같은 산소를 포함하는 가스를 첨가하는 것을 사용한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명을 실시하기 위한 장치의 1예을 나타낸 단면도.
제2도는 제1도의 장치에 에칭가스를 공급하는 공급게를 나타낸 도면.
제3도는 내지 제5도는 웨이퍼의 에칭상태를 설명하기 위한 단면도.
제6도는 에칭가스로서 HBr가스와 Cl2가스와 혼합 가스를 사용한 경우에 있어서의 유량과 폴리실리콘의 선택비와의 관계를 나타낸 그래프.
제7도는 에칭가스로서 HBr가스와 O2가스와의 혼합 가스를 사용한 경우에 있어서의 O2가스의 첨가량을 변화시킨 경우의 폴리실리콘의 에칭비, SiO2의 에칭비, 폴리실리콘의 SiO2에 대한 선택비, 및 폴리실리콘의 면내균일성을 나타낸 그래피이다.
Claims (8)
- 실리콘 함유층을 가지는 피처리물체에 있어서의 실리콘 함유층의 에칭방법에 있어 고주파 전계와 그 전계에 직교하는 전계에 의하여 마그네트론 방전을 발생시켜 에칭가스에 플라즈마를 생성하는 공정과 상기의 피처리체를 상기 플라즈마중에 노출하여 상기 실리콘 함유칭을 에칭하는 공정을 가지며 상기 에칭가스는 HBr가스, HBr가스와 Cl2가스의 혼합 가스를 주체로하는 에칭방법.
- 제1항에 있어서 에칭가스로서 HBr가스와 Cl2가스의 혼합 가스를 사용하는 경우에, HBr가스와 Cl2가스에 대한 유량비는 20/80이상인 에칭방법.
- 제2항에 있어서 HBr가스의 Cl2가스에 대한 유량비는 40/60이상인 에칭방법.
- 제1항에 있어서 실리콘 함유층은 폴리실리콘층인 에칭방법.
- 실리콘 함유층을 가지는 피처리물체에 있어서의 실리콘 함유층의 에칭방법에 있어 고주파 전계와 이 전계에 직교하는 전계에 의하여 마그네트론 방전을 발생시켜 에칭가스의 플라즈마를 생성하는 공정과 상기의 피처리체를 상기 플라즈마중에 노출하여 상기 실리콘 함유칭을 에칭하는 공정을 가지며 상기 에칭가스는 HBr가스, HBr가스와 Cl2가스의 혼합 가스 또는 HBr가스와 Cl2가스의 혼합 가스를 주체로하고 이들에 산소를 포함하는 혼합가스를 함유한 에칭방법.
- 제5항에 있어서 상기 산소를 함유하는 가스는 O2가스인 에칭방법.
- 제6항에 있어서 O2가스의 첨가량은 0.5~2%인 에칭방법.
- 제5항에 있어서 실리콘 함유층은 폴리실리콘층인 에칭방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33676891 | 1991-12-19 | ||
JP91-336768 | 1991-12-19 | ||
JP92-280963 | 1992-07-08 | ||
JP18096392A JP3179872B2 (ja) | 1991-12-19 | 1992-07-08 | エッチング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930014829A true KR930014829A (ko) | 1993-07-23 |
KR0179384B1 KR0179384B1 (ko) | 1999-10-01 |
Family
ID=26500314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920024811A KR0179384B1 (ko) | 1991-12-19 | 1992-12-19 | 에칭방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5368684A (ko) |
JP (1) | JP3179872B2 (ko) |
KR (1) | KR0179384B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160125896A (ko) * | 2015-04-22 | 2016-11-01 | 도쿄엘렉트론가부시키가이샤 | 에칭 처리 방법 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5770098A (en) * | 1993-03-19 | 1998-06-23 | Tokyo Electron Kabushiki Kaisha | Etching process |
EP0709877A4 (en) * | 1993-05-20 | 1997-11-26 | Hitachi Ltd | PLASMA TREATMENT PROCESS |
JP3172758B2 (ja) * | 1993-11-20 | 2001-06-04 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
JP3351183B2 (ja) * | 1995-06-19 | 2002-11-25 | 株式会社デンソー | シリコン基板のドライエッチング方法及びトレンチ形成方法 |
KR100230981B1 (ko) * | 1996-05-08 | 1999-11-15 | 김광호 | 반도체장치 제조공정의 플라즈마 식각 방법 |
US5910452A (en) * | 1996-05-13 | 1999-06-08 | Winbond Electronics Corporation | Method for reducing antenna effect during plasma etching procedure for semiconductor device fabrication |
TW358228B (en) * | 1996-06-08 | 1999-05-11 | Winbond Electronics Corp | Method of minimizing damage to gate dielectric layer during gate electrode plasma etching |
US6159794A (en) * | 1998-05-12 | 2000-12-12 | Advanced Micro Devices, Inc. | Methods for removing silicide residue in a semiconductor device |
JPH11330262A (ja) * | 1998-05-15 | 1999-11-30 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US6515751B1 (en) | 1999-03-11 | 2003-02-04 | Cornell Research Foundation Inc. | Mechanically resonant nanostructures |
US6514378B1 (en) | 2000-03-31 | 2003-02-04 | Lam Research Corporation | Method for improving uniformity and reducing etch rate variation of etching polysilicon |
US7972469B2 (en) | 2007-04-22 | 2011-07-05 | Applied Materials, Inc. | Plasma processing apparatus |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4450042A (en) * | 1982-07-06 | 1984-05-22 | Texas Instruments Incorporated | Plasma etch chemistry for anisotropic etching of silicon |
US4490209B2 (en) * | 1983-12-27 | 2000-12-19 | Texas Instruments Inc | Plasma etching using hydrogen bromide addition |
US4799991A (en) * | 1987-11-02 | 1989-01-24 | Motorola, Inc. | Process for preferentially etching polycrystalline silicon |
US4983253A (en) * | 1988-05-27 | 1991-01-08 | University Of Houston-University Park | Magnetically enhanced RIE process and apparatus |
US5007982A (en) * | 1988-07-11 | 1991-04-16 | North American Philips Corporation | Reactive ion etching of silicon with hydrogen bromide |
JPH03241829A (ja) * | 1990-02-20 | 1991-10-29 | Fujitsu Ltd | 半導体装置の製造方法 |
US5106767A (en) * | 1990-12-07 | 1992-04-21 | International Business Machines Corporation | Process for fabricating low capacitance bipolar junction transistor |
US5242536A (en) * | 1990-12-20 | 1993-09-07 | Lsi Logic Corporation | Anisotropic polysilicon etching process |
-
1992
- 1992-07-08 JP JP18096392A patent/JP3179872B2/ja not_active Expired - Lifetime
- 1992-12-18 US US07/993,063 patent/US5368684A/en not_active Expired - Lifetime
- 1992-12-19 KR KR1019920024811A patent/KR0179384B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160125896A (ko) * | 2015-04-22 | 2016-11-01 | 도쿄엘렉트론가부시키가이샤 | 에칭 처리 방법 |
Also Published As
Publication number | Publication date |
---|---|
JP3179872B2 (ja) | 2001-06-25 |
JPH05226297A (ja) | 1993-09-03 |
KR0179384B1 (ko) | 1999-10-01 |
US5368684A (en) | 1994-11-29 |
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