KR960701449A - 랜덤 액세스 메모리에 기초하여 구성할 수 있는 어레이(random access memory(ram) based configurable arrays) - Google Patents

랜덤 액세스 메모리에 기초하여 구성할 수 있는 어레이(random access memory(ram) based configurable arrays) Download PDF

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KR960701449A
KR960701449A KR1019950704021A KR19950704021A KR960701449A KR 960701449 A KR960701449 A KR 960701449A KR 1019950704021 A KR1019950704021 A KR 1019950704021A KR 19950704021 A KR19950704021 A KR 19950704021A KR 960701449 A KR960701449 A KR 960701449A
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ram
memory
array
memory cell
memory cells
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KR1019950704021A
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디. 프리만 리차드
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더글라스 클린트
지케드 코오포레이숀
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Publication of KR960701449A publication Critical patent/KR960701449A/ko

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)

Abstract

필드 프로그램 가능 장치는 직접 회로 기판의 동일 영역을 분할하는 전도체의 행 및 열위 2개의 분리 및 전기적으로 고립된 어레이(11,60)를 포함하는데, 하나의 어레이(11)가 램(78)("RAM")을 형성하기위해 메모리셀과 상호접속한다. 다른 어레이(60)는 메모리셀에 저장된 정보에 의해 제어되는 전체 및 일부 접촉점 스위칭 네트워크(65)를 구성 및/또는 메모리셀에 저장된 정보에 따라서 구성 및 동작할 수 있게 되는 동작 전자 회로(66)에 접속한다. 또한, 상기 메모리 어레이(11)는 동작중에 내부 신호를 용이하게 관측하게 하기위하여 상기 회로 어레이(6)의 액세스 요구 모드에 용이하게 사용한다. 바람직한 메모리 구조는 비록 메모리셀의 상태를 주기적으로 판독 및 리프세쉬하는 것이 요구되지만 현재의 DRAM 제조 기술의 고밀도 및 저비용 때문에, 동적 램("RAM")이다. 복수의 회로(21, 25, 41) 및 기술이 그것의 리프레쉬 사이클동안 인터럽션없이 메모리셀 상태의 연속전인 어설션(assertion)을 허용하여 사용된다.

Description

랜덤 액세스 메모리에 기초하여 구성할 수 있는 어레이(RANDOM ACCESS MEMORY(RAM) BASED CONFIGURABLE ARRAYS)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 다양한 태양의 완전 직접 회로의 기능적인 소자를 도시한다.
제2A도는 제1도의 직접 회로 내에 포함되는 스위칭 셀의 예의 2개의 직접 회로 칩 래이아웃을 도시한다.
제3A도는 제1도의 직접 회로내에 포함되는 논리 유닛의 예의 회로칩 래이아웃을 도시한다.
제11A도는 큰 용량성 소자를 갖는 메모리셀을 사용하는 본 발명의 실시예의 개략도이다.

Claims (2)

  1. 2개의 신호 라인 근처에 형성된 스위칭 셀로서, 시간 경과에 따라 자연적으로 손실되는 전자 전하를 저장하므로써 형성된 상태 정보를 갖는 형태의 메모리 셀과, 상기 2개의 신호 라인 사이에 접속되어 그 사이에 도전 경로를 제고하는 스위치와, 상기 메모리 셀과 상기 스위치 사이에만 전적으로 접속되어 상기 스위치가 상기 메모리 셀의 상태에 따라 상기 접속을 통해 제어될 수 있게 하는 전용 회로를 포함한 스위칭 셀과; 상기 메모리셀의 전하 레벨을 판독하고 메모리 셀의 상기 상태를 표시하는 전하를 상기 메모리 셀에 재기록하기위해 상기 메모리셀과 동작가능하게 접속되는리프레쉬 수단을 포함하는 것을 특징으로 하는 집적 회로.
  2. 제1항에 있어서, 상기 전용 회로가 상기 메모리를 판독하는 동안에 상기 메모리 제어된 스위치 상태를 유지하기 위한 수단을 포함하는 것을 특징으로 하는 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950704021A 1993-03-17 1994-03-16 랜덤 액세스 메모리에 기초하여 구성할 수 있는 어레이(random access memory(ram) based configurable arrays) KR960701449A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US3261093A 1993-03-17 1993-03-17
US08/032,610 1993-03-17
PCT/US1994/002885 WO1994022142A1 (en) 1993-03-17 1994-03-16 Random access memory (ram) based configurable arrays

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KR960701449A true KR960701449A (ko) 1996-02-24

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US (1) US5594698A (ko)
EP (1) EP0689712A4 (ko)
JP (1) JP3922653B2 (ko)
KR (1) KR960701449A (ko)
CN (1) CN1120373A (ko)
CA (1) CA2158467A1 (ko)
TW (1) TW393605B (ko)
WO (1) WO1994022142A1 (ko)

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CN1120373A (zh) 1996-04-10
CA2158467A1 (en) 1994-09-29
US5594698A (en) 1997-01-14
WO1994022142A1 (en) 1994-09-29
EP0689712A4 (en) 1997-05-28
TW393605B (en) 2000-06-11
JPH08508361A (ja) 1996-09-03
JP3922653B2 (ja) 2007-05-30
EP0689712A1 (en) 1996-01-03

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