JPH08508361A - ランダムアクセスメモリ(ram)ベースのコンフィギュラブルアレイ - Google Patents
ランダムアクセスメモリ(ram)ベースのコンフィギュラブルアレイInfo
- Publication number
- JPH08508361A JPH08508361A JP6521234A JP52123494A JPH08508361A JP H08508361 A JPH08508361 A JP H08508361A JP 6521234 A JP6521234 A JP 6521234A JP 52123494 A JP52123494 A JP 52123494A JP H08508361 A JPH08508361 A JP H08508361A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- memory
- logic
- capacitor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.2の信号線を選択的に相互接続する集積回路であって、 2の信号線の近傍に形成され、かつ 本来時間の経過とともに失われる電子的電荷をストアすることによって状態情 報が具体化される型のメモリセルと、 前記2の信号線の間に、そこに導通経路を与えるような方法で接続されたスイ ッチと、 メモリセルとスイッチとの間に排他的に接続された専用回路とを含むスイッチ ングセルを含み、前記スイッチはメモリセルの状態に従って前記接続を介して制 御可能であり、前記集積回路はさらに 前記メモリセルに動作的に結合され、メモリセルの電荷レベルを読出しかつそ の前記状態を表わす電荷をそこに再書込するためのリフレッシュ手段を含む、集 積回路。 2.前記専用回路は前記メモリの読出の間メモリ制御されたスイッチの状態を維 持する手段を含む、請求項1に記載の回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3261093A | 1993-03-17 | 1993-03-17 | |
US08/032,610 | 1993-03-17 | ||
PCT/US1994/002885 WO1994022142A1 (en) | 1993-03-17 | 1994-03-16 | Random access memory (ram) based configurable arrays |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08508361A true JPH08508361A (ja) | 1996-09-03 |
JP3922653B2 JP3922653B2 (ja) | 2007-05-30 |
Family
ID=21865844
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52123494A Expired - Fee Related JP3922653B2 (ja) | 1993-03-17 | 1994-03-16 | ランダムアクセスメモリ(ram)ベースのコンフィギュラブルアレイ |
Country Status (8)
Country | Link |
---|---|
US (1) | US5594698A (ja) |
EP (1) | EP0689712A4 (ja) |
JP (1) | JP3922653B2 (ja) |
KR (1) | KR960701449A (ja) |
CN (1) | CN1120373A (ja) |
CA (1) | CA2158467A1 (ja) |
TW (1) | TW393605B (ja) |
WO (1) | WO1994022142A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6093532A (ja) * | 1983-10-27 | 1985-05-25 | Matsushita Electric Ind Co Ltd | 基準電圧回路 |
JP2007535198A (ja) * | 2003-07-17 | 2007-11-29 | アクテル・コーポレイシヨン | フラッシュ/ダイナミックランダムアクセスメモリフィールドプログラマブルゲートアレイ |
JP2014099845A (ja) * | 2012-10-17 | 2014-05-29 | Semiconductor Energy Lab Co Ltd | プログラマブルロジックデバイス |
JP2017010606A (ja) * | 2010-08-16 | 2017-01-12 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US9673823B2 (en) | 2011-05-18 | 2017-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving semiconductor device |
JP2017174491A (ja) * | 2012-02-17 | 2017-09-28 | 株式会社半導体エネルギー研究所 | 記憶装置 |
Families Citing this family (35)
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US5317212A (en) * | 1993-03-19 | 1994-05-31 | Wahlstrom Sven E | Dynamic control of configurable logic |
US5548228A (en) * | 1994-09-28 | 1996-08-20 | Altera Corporation | Reconfigurable programmable logic device having static and non-volatile memory |
US5847577A (en) * | 1995-02-24 | 1998-12-08 | Xilinx, Inc. | DRAM memory cell for programmable logic devices |
US5581501A (en) * | 1995-08-17 | 1996-12-03 | Altera Corporation | Nonvolatile SRAM cells and cell arrays |
US6005806A (en) * | 1996-03-14 | 1999-12-21 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US5925904A (en) * | 1996-04-03 | 1999-07-20 | Altera Corporation | Two-terminal electrically-reprogrammable programmable logic element |
US5949710A (en) | 1996-04-10 | 1999-09-07 | Altera Corporation | Programmable interconnect junction |
US5959891A (en) * | 1996-08-16 | 1999-09-28 | Altera Corporation | Evaluation of memory cell characteristics |
US6018476A (en) * | 1996-09-16 | 2000-01-25 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6236597B1 (en) | 1996-09-16 | 2001-05-22 | Altera Corporation | Nonvolatile memory cell with multiple gate oxide thicknesses |
US5914904A (en) | 1996-10-01 | 1999-06-22 | Altera Corporation | Compact electrically erasable memory cells and arrays |
DE19654846A1 (de) * | 1996-12-27 | 1998-07-09 | Pact Inf Tech Gmbh | Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.) |
US6157566A (en) * | 1997-08-20 | 2000-12-05 | Micron Technology, Inc. | Reduced leakage DRAM storage unit |
US6005801A (en) | 1997-08-20 | 1999-12-21 | Micron Technology, Inc. | Reduced leakage DRAM storage unit |
US6201734B1 (en) | 1998-09-25 | 2001-03-13 | Sandisk Corporation | Programmable impedance device |
US6882553B2 (en) * | 2002-08-08 | 2005-04-19 | Micron Technology Inc. | Stacked columnar resistive memory structure and its method of formation and operation |
US7129749B1 (en) * | 2004-10-27 | 2006-10-31 | Lattice Semiconductor Corporation | Programmable logic device having a configurable DRAM with transparent refresh |
US7593284B2 (en) * | 2007-10-17 | 2009-09-22 | Unity Semiconductor Corporation | Memory emulation using resistivity-sensitive memory |
US7911229B2 (en) * | 2008-09-26 | 2011-03-22 | Siliconblue Technologies Corporation | Programmable signal routing systems having low static leakage |
US20100205367A1 (en) * | 2009-02-09 | 2010-08-12 | Ehrlich Richard M | Method And System For Maintaining Cache Data Integrity With Flush-Cache Commands |
KR20110029811A (ko) * | 2009-09-16 | 2011-03-23 | 삼성전자주식회사 | 수직 나노 와이어를 포함하는 정보 저장 장치 |
KR101893332B1 (ko) * | 2009-11-13 | 2018-08-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 구동 방법 |
KR101789975B1 (ko) | 2010-01-20 | 2017-10-25 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
US8570785B2 (en) * | 2010-05-26 | 2013-10-29 | Hewlett-Packard Development Company | Reading a memory element within a crossbar array |
US8705307B2 (en) | 2011-11-17 | 2014-04-22 | International Business Machines Corporation | Memory system with dynamic refreshing |
US8953362B2 (en) * | 2012-05-11 | 2015-02-10 | Adesto Technologies Corporation | Resistive devices and methods of operation thereof |
JP6250955B2 (ja) * | 2012-05-25 | 2017-12-20 | 株式会社半導体エネルギー研究所 | 半導体装置の駆動方法 |
CN104756191A (zh) * | 2012-09-11 | 2015-07-01 | Adesto技术公司 | 阻性器件及其操作方法 |
US9954533B2 (en) * | 2014-12-16 | 2018-04-24 | Samsung Electronics Co., Ltd. | DRAM-based reconfigurable logic |
KR102420735B1 (ko) | 2016-08-19 | 2022-07-14 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 전원 제어 방법 |
US10732866B2 (en) | 2016-10-27 | 2020-08-04 | Samsung Electronics Co., Ltd. | Scaling out architecture for DRAM-based processing unit (DPU) |
US10180808B2 (en) * | 2016-10-27 | 2019-01-15 | Samsung Electronics Co., Ltd. | Software stack and programming for DPU operations |
US9922696B1 (en) * | 2016-10-28 | 2018-03-20 | Samsung Electronics Co., Ltd. | Circuits and micro-architecture for a DRAM-based processing unit |
FR3076051B1 (fr) * | 2017-12-26 | 2020-01-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Circuit memoire |
US11373695B2 (en) * | 2019-12-18 | 2022-06-28 | Micron Technology, Inc. | Memory accessing with auto-precharge |
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JPS58188154A (ja) * | 1982-04-28 | 1983-11-02 | Toshiba Corp | ダイナミック形記憶装置 |
JPS63166091A (ja) * | 1986-12-27 | 1988-07-09 | Sony Corp | 半導体記憶装置 |
JPH02291720A (ja) * | 1989-05-01 | 1990-12-03 | Kawasaki Steel Corp | プログラム可能な論理デバイス |
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-
1994
- 1994-03-16 WO PCT/US1994/002885 patent/WO1994022142A1/en not_active Application Discontinuation
- 1994-03-16 KR KR1019950704021A patent/KR960701449A/ko not_active Application Discontinuation
- 1994-03-16 CN CN94191624A patent/CN1120373A/zh active Pending
- 1994-03-16 EP EP94911629A patent/EP0689712A4/en not_active Withdrawn
- 1994-03-16 JP JP52123494A patent/JP3922653B2/ja not_active Expired - Fee Related
- 1994-03-16 CA CA002158467A patent/CA2158467A1/en not_active Abandoned
- 1994-05-24 TW TW083104685A patent/TW393605B/zh not_active IP Right Cessation
- 1994-11-04 US US08/334,885 patent/US5594698A/en not_active Expired - Lifetime
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JPH02291720A (ja) * | 1989-05-01 | 1990-12-03 | Kawasaki Steel Corp | プログラム可能な論理デバイス |
Cited By (8)
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JPS6093532A (ja) * | 1983-10-27 | 1985-05-25 | Matsushita Electric Ind Co Ltd | 基準電圧回路 |
JP2007535198A (ja) * | 2003-07-17 | 2007-11-29 | アクテル・コーポレイシヨン | フラッシュ/ダイナミックランダムアクセスメモリフィールドプログラマブルゲートアレイ |
JP2017010606A (ja) * | 2010-08-16 | 2017-01-12 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US9673823B2 (en) | 2011-05-18 | 2017-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving semiconductor device |
US10135446B2 (en) | 2011-05-18 | 2018-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving semiconductor device |
US11356097B2 (en) | 2011-05-18 | 2022-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving semiconductor device |
JP2017174491A (ja) * | 2012-02-17 | 2017-09-28 | 株式会社半導体エネルギー研究所 | 記憶装置 |
JP2014099845A (ja) * | 2012-10-17 | 2014-05-29 | Semiconductor Energy Lab Co Ltd | プログラマブルロジックデバイス |
Also Published As
Publication number | Publication date |
---|---|
EP0689712A1 (en) | 1996-01-03 |
CA2158467A1 (en) | 1994-09-29 |
CN1120373A (zh) | 1996-04-10 |
WO1994022142A1 (en) | 1994-09-29 |
TW393605B (en) | 2000-06-11 |
EP0689712A4 (en) | 1997-05-28 |
US5594698A (en) | 1997-01-14 |
JP3922653B2 (ja) | 2007-05-30 |
KR960701449A (ko) | 1996-02-24 |
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