KR950034738A - 박막 트랜지스터의 구조 및 제조방법 - Google Patents

박막 트랜지스터의 구조 및 제조방법 Download PDF

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KR950034738A
KR950034738A KR1019940010411A KR19940010411A KR950034738A KR 950034738 A KR950034738 A KR 950034738A KR 1019940010411 A KR1019940010411 A KR 1019940010411A KR 19940010411 A KR19940010411 A KR 19940010411A KR 950034738 A KR950034738 A KR 950034738A
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gate electrode
semiconductor layer
thin film
insulating film
gate
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KR0136931B1 (ko
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최종문
조석원
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문정환
금성일렉트론 주식회사
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Priority to DE4428312A priority patent/DE4428312C2/de
Priority to US08/296,172 priority patent/US5432102A/en
Priority to JP06295999A priority patent/JP3108752B2/ja
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Priority to US08/788,204 priority patent/US5723879A/en
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

본 발명은 반도체소자인 박막 트랜지스터에 관한 것으로, 특히 SRAM의 메모리셀(Memory Cell)에 적당하도록 한 박막 트랜지스터의 구조 및 제조방법에 관한 것이다.
이와 같은 본 발명의 박막 트랜지스터의 구조는 기판상에 형성되는 게이트전극, 상기 게이트전극 일측에 형성되는 절연막 사이드월, 상기 기판과 게이트전극 및 사이드월에 걸쳐 형성되는 게이트 절연막, 상기 게이트 절연막위에 형성되는 반도체층, 상기 게이트전극 및 사이드월 상측과 게이트전극 타측 기판 상측의 반도체층에 선택적으로 형성되는 불순물확산 영역, 상기 게이트전극 타측면의 반도체층에 형성되는 채널영역을 포함하여 구성되고, 본 발명의 박막 트랜지스터의 제조방법은 기판 상에 게이트 전극용 반도체층을 형성하는 공정, 게이트 전극 영역을 정의하여 게이트 전극 일측을 중심으로 게이트 전극 영역이 아닌 부분의 상기 반도체층을 제거하는 공정, 상기 반도체층 일측에 절연막 사이드월(Side Wall)을 형성하는 공정, 게이트 전극타측을 중심으로 게이트 전극 타측을 중심으로 게이트 전극 영역이 아닌 부분의 반도체층을 제거하여 게이트 전극을 형성하는 공정, 전면에 게이트 절연막과 반도체층을 차례로 형성하는 공정, 상기 반도체층에 수직으로 불순물이온 주입하여 소오스 및 드레인영역을 형성하는 공정을 포함하여 이루어진 것이다.

Description

박막 트랜지스터의 구조 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (a)∼(e)는 본 발명의 박막 트랜지스터 공정단면도, 제3도는 본 발명의 박막 트랜지스터 사시도, 제4도는 본 발명에 따라 이온주입 농도 설명도.

Claims (11)

  1. 기판, 상기 기판상에 형성되는 게이트전극, 상기 게이트전극 일측에 형성되는 절연막 사이드월, 상기 기판과 게이트전극 및 사이드월에 걸쳐 형성되는 게이트 절연막, 상기 게이트 절연막위에 형성되는 반도체층, 상기 게이트전극 및 사이드월 상측과 게이트전극 타측 절연기판 상측의 반도체층에 선택적으로 형성되는 불순물확산 영역, 상기 게이트전극 타측면의 반도체층에 형성되는 채널영역을 포함하여 구성됨을 특징으로 하는 박막 트랜지스터의 구조.
  2. 제1항에 있어서, 게이트전극과 게이트 절연막 사이에 캡게이트 절연막이 더 형성됨을 특징으로 하는 박막 트랜지스터의 구조.
  3. 제2항에 있어서, 캡게이트 절연막의 두께는 상응하도록 채널영역에서 불순물확산 영역과 게이트전극이 옵셋됨을 특징으로 하는 박막 트랜지스터의 구조.
  4. 제1항에 있어서, 기판위에 절연막이 더 형성됨을 특징으로 하는 박막 트랜지스터의 구조.
  5. 기판 상에 게이트 전극용 반도체층을 형성하는 공정, 게이트 전극 영역을 정의하여 게이트 전극 일측을 중심을 게이트 전극 영역이 아닌 부분의 상기 반도체층을 선택적으로 제거하는 공정, 상기 반도체층 일측에 절연막 사이드월(Side Wall)을 형성하는 공정, 게이트 전측 타측을 중심으로 게이트 전극 영역이 아닌 부분의 반도체층을 선택적으로 제거하여 게이트 전극을 형성하는 공정, 전면에 게이트 절연막과 반도체층을 차례로 형성하는 공정, 상기 반도체층에 수직으로 불순물이온 주입하여 소오스 및 드레인영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 박막 트랜지스터의 제조방법.
  6. 제5항에 있어서, 게이트전극상에 캡게이트 절연막을 더 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.
  7. 제5항에 있어서, 불순물이온 주입은 p채널 트랜지스터인 경우 p형 불순물이온을 5kev∼20kev 에너지로 1×1014∼1×1016atoms/㎠의 농도로 이온주입함을 특징으로 하는 박막 트랜지스터의 제조방법.
  8. 제5항에 있어서, 불순물이온 주입은 n채널 트랜지스터인 경우 n형 불순물이온을 10kev∼50kev 에너지로 1×1014∼1×1016atoms/㎠의 농도로 이온주입함을 특징으로 하는 박막 트랜지스터의 제조방법.
  9. 제5항에 있어서, 반도체층은 폴리시리콘을 사용함을 특징으로 하는 박막 트랜지스터의 제조방법.
  10. 제5항 또는 제9항에 있어서, 반도체층의 두께는 200∼500A으로 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.
  11. 제6항에 있어서, 캡게이트 절연막의 두께는 게이트전극과 불순물확산 영역간의 옵셋되는 길이에 따라 결정됨을 특징으로 하는 박막 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940010411A 1994-05-12 1994-05-12 박막 트랜지스터의 구조 및 제조방법 KR0136931B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019940010411A KR0136931B1 (ko) 1994-05-12 1994-05-12 박막 트랜지스터의 구조 및 제조방법
DE4428312A DE4428312C2 (de) 1994-05-12 1994-08-10 Dünnfilmtransistor und Verfahren zu seiner Herstellung
US08/296,172 US5432102A (en) 1994-05-12 1994-08-29 Method of making thin film transistor with channel and drain adjacent sidewall of gate electrode
JP06295999A JP3108752B2 (ja) 1994-05-12 1994-11-07 薄膜トランジスタ及びその製造方法
US08/788,204 US5723879A (en) 1994-05-12 1997-01-24 Thin film transistor with vertical channel adjacent sidewall of gate electrode and method of making

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KR1019940010411A KR0136931B1 (ko) 1994-05-12 1994-05-12 박막 트랜지스터의 구조 및 제조방법

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KR0136931B1 KR0136931B1 (ko) 1998-04-24

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DE4428312A1 (de) 1995-11-23
DE4428312C2 (de) 2003-02-20
KR0136931B1 (ko) 1998-04-24
JPH07321340A (ja) 1995-12-08
US5723879A (en) 1998-03-03
US5432102A (en) 1995-07-11
JP3108752B2 (ja) 2000-11-13

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