KR980006490A - 반도체 소자 및 그의 제조방법 - Google Patents

반도체 소자 및 그의 제조방법 Download PDF

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Publication number
KR980006490A
KR980006490A KR1019960026296A KR19960026296A KR980006490A KR 980006490 A KR980006490 A KR 980006490A KR 1019960026296 A KR1019960026296 A KR 1019960026296A KR 19960026296 A KR19960026296 A KR 19960026296A KR 980006490 A KR980006490 A KR 980006490A
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South Korea
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forming
region
semiconductor substrate
predetermined
gate electrode
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KR1019960026296A
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English (en)
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KR100233558B1 (ko
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김재갑
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김주용
현대전자산업 주식회사
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Priority to KR1019960026296A priority Critical patent/KR100233558B1/ko
Priority to TW086108423A priority patent/TW416113B/zh
Priority to JP9183142A priority patent/JPH1070272A/ja
Priority to GB9713545A priority patent/GB2314973B/en
Priority to DE19727491A priority patent/DE19727491A1/de
Priority to CNB971138710A priority patent/CN1136613C/zh
Publication of KR980006490A publication Critical patent/KR980006490A/ko
Application granted granted Critical
Publication of KR100233558B1 publication Critical patent/KR100233558B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 반도체 소자 및 그 제조방법을 개시한다. 개시한 본 발명은,필드 절연막 주변에 P형의 불순물 결핍층의 형성을 발생코자, 필드 절연막중 액티브 영역의 케이트 예정 영역의 주변에 웰 영역 및 누설 방지층을 P형의 불순물로 형성하므로써, P형의 불순물 결핍층이 형성되지 않는다.
이로써, 이후의 반도체 소자의 소오스 드레인 영역의 형성시, 누설 전류가 최소화 된다.

Description

반도체 소자 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4a도 및 제4b도는 본 발명의 제1 실시예에 따른 N모스 트랜지스터의 제조방법을 설명하기 위한 도면.

Claims (9)

  1. P형의 반도체 기판; 상기 반도체 기판에 필드 절연막을 형성함에 의하여 구축되며, 반도체 소자가 형성되는 액티브 영역; 상기 필드 절연막 하부및 반도체 기판의 예정 영역에 형성되는 P웰 영역; 반도체 기판의 소정 부분을 지나며, 문턱 전압 이상의 전압이 인가되면, 턴온되는 게이트 전극; 상기 액티브 영역 중 게이트 전극 하부의 액티브 영역은 P웰 영역쪽으로 일정 폭만큼 확장되도록 형성되는 것을 특징으로 하는 반도체 소자.
  2. 반도체 기판의 소정 부분에 소자와 소자를 분리키 위한 필드 절연막을 형성하여, 액티브 영역을 형성하는 단계; 상기 반도체 기판의 소정 영역에 P웰을 형성하는 단계; 결과물 상부의 소정 영역에 게이트 전극을 형성하는 단계를 포함하며, 상기 엑티브 영역 형성단계에서, 게이트 전극 예정 영역에 해당하는 액티브 영역은 P웰 영역 예정 영역으로 일부분 확장되도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  3. 제2항에 있어서, 상기 P웰 형성 단계와 게이트 전극 형성 단계사이에, 문턱전압 조절 이온을 주입하는 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
  4. 제3항에 있어서, 상기 문턱 전압 조절 이온은 보론(boron)을 5 ×1011~5 ×1012ion/㎤의 농도와 약 10 내지 50KeV에 의하여 이온 주입하는 것을 특징으로 하는 반도체 소자의 제조방법.
  5. 제3항에 있어서, 상기 문턱 전압 조절 이온은 BF3를 5 ×1011~5 ×1012ion/㎤의 농도와 약 30 내지 80KeV에 의하여 이온 주입하는 것을 특징으로 하는 반도체 소자의 제조방법.
  6. 반도체 기판의 소정 부분에 P웰을 형성하는 단계; 반도체 기판의 소자 분리 예정 영역에 필드 절연막을 형성하는 단계; 상기 필드 절연막을 감싸도록 P웰 영역내의 소정 부분에 누설 전류 방지층을 형성하는 단계; 상기 구조물 상부에 게이트 전극을 형성하는 단계를 포함하며, 상기 누설 전류 방지층은 게이트 전극이 형성되는 영역에 형성된 필드 절연막의 하부를 감싸도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  7. 제6항에 있어서, 상기 누설 방지층은 P형의 불순물을 이온 주입하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  8. 제6항에 있어서, 상기 누설 방지층은 보론 원자를 약 60 내지 150KeV의 에너지 범위와 1 ×1012~1 ×1013ion/㎤의 농도로 이온 주입하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  9. 제6항에 있어서, 상기 P웰은 보론 원자를 약 50 내지 150KeV의 에너지 범위와 5 ×1012~5 ×1013ion/㎤의 농도로 이온 주입 및 확산하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
KR1019960026296A 1996-06-29 1996-06-29 반도체 소자의 제조방법 KR100233558B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019960026296A KR100233558B1 (ko) 1996-06-29 1996-06-29 반도체 소자의 제조방법
TW086108423A TW416113B (en) 1996-06-29 1997-06-17 Semiconductor device and its fanufacturing method
JP9183142A JPH1070272A (ja) 1996-06-29 1997-06-24 半導体装置及びその製造方法
GB9713545A GB2314973B (en) 1996-06-29 1997-06-26 Semiconductor device and its manufacturing method
DE19727491A DE19727491A1 (de) 1996-06-29 1997-06-27 Halbleitervorrichtung und Verfahren zu deren Herstellung
CNB971138710A CN1136613C (zh) 1996-06-29 1997-06-28 半导体装置及其制造方法

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Application Number Priority Date Filing Date Title
KR1019960026296A KR100233558B1 (ko) 1996-06-29 1996-06-29 반도체 소자의 제조방법

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KR980006490A true KR980006490A (ko) 1998-03-30
KR100233558B1 KR100233558B1 (ko) 1999-12-01

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JP (1) JPH1070272A (ko)
KR (1) KR100233558B1 (ko)
CN (1) CN1136613C (ko)
DE (1) DE19727491A1 (ko)
GB (1) GB2314973B (ko)
TW (1) TW416113B (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7304354B2 (en) * 2004-02-17 2007-12-04 Silicon Space Technology Corp. Buried guard ring and radiation hardened isolation structures and fabrication methods
US8278719B2 (en) 2005-10-14 2012-10-02 Silicon Space Technology Corp. Radiation hardened isolation structures and fabrication methods
JP4288355B2 (ja) * 2006-01-31 2009-07-01 国立大学法人北陸先端科学技術大学院大学 三値論理関数回路
WO2007108104A1 (ja) * 2006-03-20 2007-09-27 Fujitsu Limited 半導体装置及びその製造方法
JP2009267027A (ja) * 2008-04-24 2009-11-12 Seiko Epson Corp 半導体装置及びその製造方法
US10038058B2 (en) 2016-05-07 2018-07-31 Silicon Space Technology Corporation FinFET device structure and method for forming same

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Publication number Priority date Publication date Assignee Title
GB2084794B (en) * 1980-10-03 1984-07-25 Philips Electronic Associated Methods of manufacturing insulated gate field effect transistors
JPH0693494B2 (ja) * 1984-03-16 1994-11-16 株式会社日立製作所 半導体集積回路装置の製造方法
JPS61292358A (ja) * 1985-06-19 1986-12-23 Fujitsu Ltd Ｍｉｓ型電界効果トランジスタの製造方法
JPS62200767A (ja) * 1986-02-28 1987-09-04 Toshiba Corp Ｍｏｓ型半導体装置
JPS6425438A (en) * 1987-07-21 1989-01-27 Sony Corp Manufacture of semiconductor device
JPH0235778A (ja) * 1988-07-26 1990-02-06 Seiko Epson Corp 半導体装置
US5525823A (en) * 1992-05-08 1996-06-11 Sgs-Thomson Microelectronics, Inc. Manufacture of CMOS devices
US5396096A (en) * 1992-10-07 1995-03-07 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US5432107A (en) * 1992-11-04 1995-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor fabricating method forming channel stopper with diagonally implanted ions
JPH07135317A (ja) * 1993-04-22 1995-05-23 Texas Instr Inc <Ti> 自己整合型シリサイドゲート

Also Published As

Publication number Publication date
GB2314973B (en) 2001-09-19
DE19727491A1 (de) 1998-01-02
KR100233558B1 (ko) 1999-12-01
TW416113B (en) 2000-12-21
JPH1070272A (ja) 1998-03-10
CN1173739A (zh) 1998-02-18
CN1136613C (zh) 2004-01-28
GB9713545D0 (en) 1997-09-03
GB2314973A (en) 1998-01-14

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