GB2314973A - Semiconductor device with low threshold voltage - Google Patents

Semiconductor device with low threshold voltage Download PDF

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Publication number
GB2314973A
GB2314973A GB9713545A GB9713545A GB2314973A GB 2314973 A GB2314973 A GB 2314973A GB 9713545 A GB9713545 A GB 9713545A GB 9713545 A GB9713545 A GB 9713545A GB 2314973 A GB2314973 A GB 2314973A
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United Kingdom
Prior art keywords
substrate
ions
insulating layer
active region
threshold voltage
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Granted
Application number
GB9713545A
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GB9713545D0 (en
GB2314973B (en
Inventor
Jae Kap Kim
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Publication of GB9713545D0 publication Critical patent/GB9713545D0/en
Publication of GB2314973A publication Critical patent/GB2314973A/en
Application granted granted Critical
Publication of GB2314973B publication Critical patent/GB2314973B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

Abstract

A semiconductor device with a low threshold voltage, e.g. a MOS transistor, includes a semiconductor substrate 31 of a predetermined conductivity type; field insulating regions 32 formed on the substrate; an active region AA defined in the substrate by the field insulating regions; impurity regions 33 formed in the substrate under and inwardly of the field insulating regions 32, and having the same conductivity type as that of the substrate;voltage adjustment ions 100 implanted in the substrate; a gate insulating layer 34 formed on the substrate; and a gate pattern 35 formed on the gate insulating layer 34 and field insulating regions 32. The active area AA is extended by a distance AA' so that in overlies the regions 32, thereby avoiding formation of a depletion region which would result in leakage current.

Description

2314973 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to semiconductor device and its manufacturing method, and more particularly, to a MOS transistor with a low threshold voltage and its manufacturing method.
Discussion of Related Art As semiconductor devices become more highly integrated and their functions become more complex, they are required to have more specific functions. For this purpose, a MOS transistor having relatively low threshold voltages is employed to minimize the voltage between a source and a drain and enhance electrical characteristics of the MOS transiszor, so --ha7- the function of the semiconductor device is enhanced.
To achieve a,4-MOS transistor having a low threshold voltaae, an 1%-MOS z-1-ansiszor is formed, and P type impurity ions for conzrolling z.lie threshold voltage are count-doped in a subszra::e to lower the threshold voltage of the NMOS transis-L-c--. The 7nchi-lity of electrons, however, is decreased because cf the increase of the doped P type imi3urit-v -ons.
Moreover, P type impurity ions for controlling the threshold voltage are implanted in the initial P type semiconductor substrate having no P well, so that the threshold voltage of the NMOS transistor is decreased.
Namely, because the concentration of the P type impurity ion in the initial P type substrate is lower than that of the P well, the NMOS transistor formed in the initial substrate has a relatively lower threshold voltage compared the NMOS transistor formed in the P well.
FIG. 1 is a top view of the NMOS transistor having low threshold voltage.
As illustrated in FIG. 1, the active region A of the NMOS transistor having a low threshold voltage is defined on the initial P type substrate (not shown) A P well 3 is formed at a predetermined interval from the active region A, so that an active region A' surrounding the active region A is defined. A gate 5 crossing the center of those active region A and A, and extending to the P well 2 in some portion, is formed on the active region A and A'.
FIG. 2 is a sectional view taken along lines II-III of FIG. 1, illustrating a manufacturing method of a semiconductor device having the low threshold voltage.
As illustrated in FIG. 2, a f ield oxide layer 2 is formed on the initial P type semiconductor substrate 1. A P well 3 is formed in the substrate 1, excluding the NMOS transistor region having low threshold voltage, so that the 2 active region A and A' is defined. P type impurity ions for controlling the threshold voltage 10 are implanted in the substrate 1. A gate insulating layer 4 is formed on the active region A. A gate 5 is formed on the substrate 1. N type impurity ions are implanted in the active region A of both sides of the gate 5 to form a source and drain(not shown).
In the NMOS transistor, a depletion layer 20 of the P type impurity ions is formed in the active region A' under the field oxide layer 3 under the gate 5, after the P type impurity ions for adjusting the threshold voltage 10 are implanted in the substrate 1. The depletion layer 20 generates a leakage current between the source and drain during the operation of the NMOS transistor, so that the is electrical characteristics of the device is degraded.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a Mos transis-cr and its manufacturing method that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An objecz of the present invention is to provide a MOS -ransisr-cr and ---s manufacturing method, the MOS transistor having low --hresho-ld voltages to prevent a leakage current due to impurity depletion in an active region.
3 To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device with low threshold voltage is provided that includes: a semiconductor substrate of a predetermined conductivity type; a field insulating layer formed on the substrate; an active region defined in the substrate by the field insulating layer; an impurity region formed in the substrate to surround the field insulating layer, and having the same conductivity type as that of the substrate; a gate insulating layer formed on the substrate; and a gate pattern formed on the gate and field insulating layers.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for manufacturing a semiconductor device having low threshold voltage is provided that includes the steps of: defining an active region by forming a field insulating layer on a semiconductor substrate of a predetermined conductivity type; forming an impurity region of the same conductivity type as that of the substrate, in the substrate, to surround the under of the field insulating layer; implanting threshold voltage adjustment ions in the substrate; forming a gate insulating layer on the substrate; and forming a gate pattern on the gate insulating layer and field insulating layers.
4 It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
In the drawings:
is FIG. 1 is a top view of a conventional NMOS transistor having low threshold voltages; FIG. 2 is a sectional view of the conventional NMOS transiszor having low threshold voltages; FIG. 3 is a top view of an NMOS transistor having low threshold vc!T--ages according to one embodiment of the inventicn; FIGS. 4A to 4C are sectional views illustrating the manuf ac -:,.:ring procedures of the NMOS transistor having threshc-d voltages according to one embodiment of the invenzcn; and -T(--S. 5A and 53 are sectional views illustrating the manufacturing procedures of the NMOS transistor having threshold voltages according to another embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
As illustrated in FIG. 3, an active region AA of an NMOS transistor having a low threshold voltage is defined in an initial P type semiconductor substrate (not shown).
Here, the active region AA has protrusion AA' protruding on both sides of the central part in the active region AA. P well 33 having predetermined portions overlapping with the protrusion AA' of the active region AA is formed on the substrate at a predetermined interval from the active region AA. There is formed a gate 35 extending to the protrusion AA' on the central part of the active region AA and the P well 33. That is, the predetermined portions of the active region AA extend to the P well 33 under the gate 35.
FIGS. 4A to 4C are sectional views taken along lines IV-IV' of FIG. 3. Manufacturing procedures of the NMOS transistor of the invention will now be described below with reference to FIGS. 4A and 4C.
6 As illustrated in FIG. 4A, the field oxide layer 32 are formed on predetermined regions the initial P type semiconductor substrate 31 to define the active region AA of the NMOS transistor having low threshold voltage. Here, as the parts of the field oxide layer 32 are formed at a greater interval from each other as shown in the active region AA in the drawing, so that they are extended more than the conventional active region A and A' by a predetermined distance. Thereafter, a screen insulating layer 90 is formed on the substrate.
As illustrated in FIG. 43, the P well 33 is formed in the substrate to include the active region, namely, the protrusion AA of FIG. 3, extending and surrounding the field oxide layer 32. Thereafter, P type impurity ions for adjusting the threshold vcltaae 100, preferably, B ions are implanted in the active regions AA and AA' at a /CM2 concentration of SxlO" to 5x10-2 ions and at an energy of 10-50 KeV. Alternativeiv, 3F, ions can be implanted by 5xiO12 a concentration of 5xio to- ions/cm' and at an energy of 30-80 KeV. As a result, the threshold voltage becomes about 0.2-0.4V.
As illuszrated in FIG. 41C, the screen oxide layer 90 is removed, and the gate insulating layer 34 is formed on -he portion of the substraze 31. The gate 35 is formed on the substrate.
in this e7bcdiment of t,--e invention, the active region 7 AA under the field oxide layer 32 under the gate 35 of the
NMOS transistor extends to the P well 33. Therefore, the depletion of the P type impurity ion is prevented at the active region AA of the initial P type substrate 31 which has a lower concentration of P type impurity ion than that of the P well 33.
FIGS. 5A and 5B are sectional views of the NMOS transistor corresponding to line III-III' of FIG. 3, in accordance to another embodiment of the invention.
Hereinafter, there follows a description of a method for manufacturing the NMOS transistor having the relatively low threshold voltage at the state where the P well is formed on the substrate.
As illustrated in FIG. SA, P type impurity ions, is preferably, B ions are implanted in a initial P type semiconductor substrate S1 where the NMOS transistor will be formed by a concentration of 5XIO12 to 5xl 013 ions/cm' and at an energy of 50-150 KeV. Thereafter, P wells 52 are formed by a diffusion process. Accordingly, the threshold voltage of the NMOS transistor is about 0.2-0.4V. A field oxide layer 53 is formed on the P well 52 to define the active region AA. Here, as the parts of the field oxide layer 52 are formed at a greater interval from each other as shown in the active region AA in the drawing, so that they are extended more than the conventional active region A and A' by a predetermined distance. Thereafter, a screen 8 insulating layer 54 is the substrate.
As illustrated in FIG. 5D, P type impurity regions 55a and 55b are formed by ion implantation to surround the field oxide layer 53 and include the protrusion AA' of the active region AA. The ion implantation is performed by implantation P type impurity ions, preferably, B ions, by 1X1012 to 1X101.3 a concentration of ions/cm and at an energy 60-150 KeV. Here, the P type impurity regions 55a and 55b are not formed at predetermined a source and drain of the active region AA (refer to FIG. 3). That is, the protrusion AA' of the active region AA is made of the P type impurizy regions 55a and 55b. The screen oxide layer 54 is removed, and the gate insulating layer 56 is formed on the actve region AA. A gate 57 is formed on the is substrate 51.
In this embodiment of the invention, the active region AA under the field oxide layer 53 under the gate 57 of the
NMOS transistor exzends to the P type impurity region.
Therefore, --he deplezion of the P type impurity ion is prevented az the ac--'ve region AA of the P well which has lower concentration of: P type impurity ion than that of the P type impurity reg-Lon.
As described above, the invention prevents the depletion c: --he impurity ions generated in the active region ldnder the gate of the transistor having lower threshold voltage. Therefore, the leakage current 9 generated between the source and drain during the operation of the transistor are prevented, so that the characteristic of the transistor having lower threshold voltage is enhanced.
It will be apparent to those skilled in the art that various modifications and variations can be made in the semiconductor device and its manufacturing method of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (8)

  1. What is claimed is:
    A semiconductor device with low threshold voltages, comprising:
    a semiconductor substrate of a predetermined conductivity type; a field insulating layer formed on the substrate; an active region defined in the substrate by the field insulating layer; an impurity region formed in the substrate to surround the field insulating layer, and having the same conductivity type as that of the substrate; a gate insulating layer formed on the substrate; and a gate pattern formed on the gate and field insulating is layers.
  2. 2. A method for manufacturing a semiconductor device having low thresh--ld voltages, comprising the steps of:
    defining an active region by forming a field layer on a semiconductor substrate of a predetermined conductivity ty pe; -C forming an impurity region of the same conductivity type as that of the substrate, in the substrate, to surround the under of the field insulating layer; implanting zh-reshold voltage adjustment ions in the substrate; 111 forming a gate insulating layer on the substrate; and forming a gate pattern on the gate insulating layer and field insulating layers.
  3. 3. The method as claimed in claim 2, wherein the semiconductor substrate is an initial substrate where the impurity ions are not doped.
  4. 4. The method as claimed in claim 3, wherein the step of implanting the threshold voltage adjustment ions is performed by implanting B ions by a concentration of 5x1011 to 5xlO" ions /CM2 and at an energy of 10-50 KeV.
  5. 5. The method as claimed in claim 3, wherein the step of implanting the threshold voltage adjustment ions is performed by implanting BF2 ions by a concentration of SxlO" to 5 X1012 ions /CM2 and at an energy of 30-80 KeV.
  6. 6. The method as claimed in claim 2, wherein a well is formed in the semiconductor substrate.
  7. 7. The method as claimed in claim 6, wherein the well is formed by implanting B ions by a concentration of 5 X1012 to SX1013 ions /CM2 and at an energy of 50-150 KeV.
  8. 8. The method as claimed in claim 6, wherein the 12 impurity region is formed by implanting B ions by a concentration of 1x101' to 1x101' ions /CM2 and at an energy of 60-150 KeV.
    13
GB9713545A 1996-06-29 1997-06-26 Semiconductor device and its manufacturing method Expired - Fee Related GB2314973B (en)

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KR1019960026296A KR100233558B1 (en) 1996-06-29 1996-06-29 Manufacturing method of a semiconductor device

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GB2314973A true GB2314973A (en) 1998-01-14
GB2314973B GB2314973B (en) 2001-09-19

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KR (1) KR100233558B1 (en)
CN (1) CN1136613C (en)
DE (1) DE19727491A1 (en)
GB (1) GB2314973B (en)
TW (1) TW416113B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093145B2 (en) 2004-02-17 2012-01-10 Silicon Space Technology Corp. Methods for operating and fabricating a semiconductor device having a buried guard ring structure
US8252642B2 (en) 2005-10-14 2012-08-28 Silicon Space Technology Corp. Fabrication methods for radiation hardened isolation structures
US10038058B2 (en) 2016-05-07 2018-07-31 Silicon Space Technology Corporation FinFET device structure and method for forming same

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JP4288355B2 (en) * 2006-01-31 2009-07-01 国立大学法人北陸先端科学技術大学院大学 Ternary logic function circuit
WO2007108104A1 (en) * 2006-03-20 2007-09-27 Fujitsu Limited Semiconductor device and its fabrication process
JP2009267027A (en) * 2008-04-24 2009-11-12 Seiko Epson Corp Semiconductor device, and method for manufacturing thereof

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GB2084794A (en) * 1980-10-03 1982-04-15 Philips Electronic Associated Methods of manufacturing insulated gate field effect transistors
EP0164449A2 (en) * 1984-03-16 1985-12-18 Hitachi, Ltd. Process for producing a semiconductor integrated circuit device including a MISFET
EP0208935A1 (en) * 1985-06-19 1987-01-21 Fujitsu Limited Narrow channel width fet
EP0239250A2 (en) * 1986-02-28 1987-09-30 Kabushiki Kaisha Toshiba Short channel MOS transistor
US5447875A (en) * 1993-04-22 1995-09-05 Texas Instruments Incorporated Self-aligned silicided gate process

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JPS6425438A (en) * 1987-07-21 1989-01-27 Sony Corp Manufacture of semiconductor device
JPH0235778A (en) * 1988-07-26 1990-02-06 Seiko Epson Corp Semiconductor device
US5525823A (en) * 1992-05-08 1996-06-11 Sgs-Thomson Microelectronics, Inc. Manufacture of CMOS devices
US5396096A (en) * 1992-10-07 1995-03-07 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US5432107A (en) * 1992-11-04 1995-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor fabricating method forming channel stopper with diagonally implanted ions

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
GB2084794A (en) * 1980-10-03 1982-04-15 Philips Electronic Associated Methods of manufacturing insulated gate field effect transistors
EP0164449A2 (en) * 1984-03-16 1985-12-18 Hitachi, Ltd. Process for producing a semiconductor integrated circuit device including a MISFET
EP0208935A1 (en) * 1985-06-19 1987-01-21 Fujitsu Limited Narrow channel width fet
EP0239250A2 (en) * 1986-02-28 1987-09-30 Kabushiki Kaisha Toshiba Short channel MOS transistor
US5447875A (en) * 1993-04-22 1995-09-05 Texas Instruments Incorporated Self-aligned silicided gate process

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093145B2 (en) 2004-02-17 2012-01-10 Silicon Space Technology Corp. Methods for operating and fabricating a semiconductor device having a buried guard ring structure
US8497195B2 (en) 2004-02-17 2013-07-30 Silicon Space Technology Corporation Method for radiation hardening a semiconductor device
US8729640B2 (en) 2004-02-17 2014-05-20 Silicon Space Technology Corporation Method and structure for radiation hardening a semiconductor device
US8252642B2 (en) 2005-10-14 2012-08-28 Silicon Space Technology Corp. Fabrication methods for radiation hardened isolation structures
US8278719B2 (en) 2005-10-14 2012-10-02 Silicon Space Technology Corp. Radiation hardened isolation structures and fabrication methods
US10038058B2 (en) 2016-05-07 2018-07-31 Silicon Space Technology Corporation FinFET device structure and method for forming same
US10615260B1 (en) 2016-05-07 2020-04-07 Silicon Space Technology Corporation Method for forming FinFET device structure

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Publication number Publication date
CN1173739A (en) 1998-02-18
KR100233558B1 (en) 1999-12-01
GB9713545D0 (en) 1997-09-03
KR980006490A (en) 1998-03-30
CN1136613C (en) 2004-01-28
TW416113B (en) 2000-12-21
JPH1070272A (en) 1998-03-10
DE19727491A1 (en) 1998-01-02
GB2314973B (en) 2001-09-19

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