JPH1070272A - Semiconductor device and fabrication thereof - Google Patents
Semiconductor device and fabrication thereofInfo
- Publication number
- JPH1070272A JPH1070272A JP9183142A JP18314297A JPH1070272A JP H1070272 A JPH1070272 A JP H1070272A JP 9183142 A JP9183142 A JP 9183142A JP 18314297 A JP18314297 A JP 18314297A JP H1070272 A JPH1070272 A JP H1070272A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- threshold voltage
- ions
- active region
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000012535 impurity Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims description 32
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000012212 insulator Substances 0.000 abstract 6
- 230000007812 deficiency Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置にかか
り、特に低いしきい電圧(threshold voltage) を有する
ＭＯＳトランジスタ及びその製造方法に関する。The present invention relates to a semiconductor device, and more particularly to a MOS transistor having a low threshold voltage and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置の高集積化及び機能の複雑化
に応じて集積回路の特殊な性能が要求される。例えば、
相対的に低いしきい電圧を有するＭＯＳトランジスタを
用いてソース及びドレインの間の電圧降下を最小化し、
ＭＯＳトランジスタの電気的特性を向上させて半導体装
置の機能を向上させる。2. Description of the Related Art As semiconductor devices become more highly integrated and their functions become more complicated, special performance of integrated circuits is required. For example,
Minimizing the voltage drop between the source and drain using a MOS transistor having a relatively low threshold voltage,
The function of the semiconductor device is improved by improving the electrical characteristics of the MOS transistor.
【０００３】一般に、低いしきい電圧を有するＮＭＯＳ
トランジスタを実現するために、ＮＭＯＳトランジスタ
を形成した後、基板にしきい電圧調節用Ｐ形不純物イオ
ンをカウントドーピング(count doping)してしきい電圧
を低めている。しかし、基板にドーピングされたＰ形不
純物の増加のため電子の移動度(mobility)が低まる。Generally, an NMOS having a low threshold voltage
In order to realize a transistor, after forming an NMOS transistor, the substrate is count-doped with P-type impurity ions for adjusting a threshold voltage to lower the threshold voltage. However, the mobility of electrons decreases due to an increase in the amount of P-type impurities doped into the substrate.
【０００４】また、低いしきい電圧を有するＮＭＯＳト
ランジスタを実現するために、Ｐウェルが形成されてい
ない初期のＰ形半導体基板にしきい電圧調節用Ｐ形不純
物イオンを注入してしきい電圧を低めている。即ち、初
期のＰ形基板がＰウェルより相対的にＰ形不純物の濃度
が低いので、初期の基板上に形成されるＮＭＯＳトラン
ジスタは相対的に低いしきい電圧を有する。Further, in order to realize an NMOS transistor having a low threshold voltage, P-type impurity ions for adjusting a threshold voltage are implanted into an initial P-type semiconductor substrate on which no P-well is formed to lower the threshold voltage. ing. That is, since the initial P-type substrate has a relatively lower concentration of P-type impurities than the P-well, the NMOS transistor formed on the initial substrate has a relatively low threshold voltage.
【０００５】図１は前述した低い電圧を有するＮＭＯＳ
トランジスタの平面図である。FIG. 1 shows an NMOS having a low voltage as described above.
FIG. 3 is a plan view of a transistor.
【０００６】図１に示すように、低いしきい電圧を有す
るＮＭＯＳトランジスタの活成領域(active region) Ａ
が初期のＰ形基板（図示せず）に定められる。活性領域
Ａから所定間隔をおいてＰウェル３が形成されて活性領
域Ａの周辺を囲む活性領域Ａ’が定められる。活性領域
Ａ，Ａ’の中央に縦の方にＰウェル２に所定部分拡張さ
れたゲート５がおかれる。As shown in FIG. 1, an active region A of an NMOS transistor having a low threshold voltage.
Are defined for the initial P-type substrate (not shown). A P-well 3 is formed at a predetermined distance from the active region A to define an active region A ′ surrounding the periphery of the active region A. In the center of the active regions A and A ', a gate 5 extended in a predetermined portion in the P well 2 is provided vertically.
【０００７】図２は図１のII−II’線に沿って切断され
た断面図であって、図２を参照して低いしきい電圧を有
するＮＭＯＳトランジスタの製造方法を説明する。FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1. Referring to FIG. 2, a method of manufacturing an NMOS transistor having a low threshold voltage will be described.
【０００８】図２に示すように、初期のＰ形半導体基板
１上にフィールド酸化膜２が形成され、低いしきい電圧
を有するＮＭＯＳトランジスタ領域を除外した基板１内
にＰウェル３が形成されて活性領域Ａ，Ａ’が定められ
る。基板１内にしきい電圧調節用Ｐ形不純物イオン１０
が注入され、活性領域Ａ上にゲート絶縁膜４が形成され
る。そして、基板１上にゲート５が予定された形態に形
成され、図示してはいない、ゲート５の両側の活性領域
ＡにＮ形不純物イオンが注入されてソース及びドレイン
が形成される。As shown in FIG. 2, a field oxide film 2 is formed on an initial P-type semiconductor substrate 1, and a P well 3 is formed in the substrate 1 excluding an NMOS transistor region having a low threshold voltage. Active regions A and A 'are defined. P-type impurity ions 10 for adjusting threshold voltage in substrate 1
Is implanted to form gate insulating film 4 on active region A. Then, a gate 5 is formed on the substrate 1 in a predetermined form, and N-type impurity ions (not shown) are implanted into the active regions A on both sides of the gate 5 to form a source and a drain.
【０００９】[0009]
【発明が解決しようとする課題】しかし、前記ＮＭＯＳ
トランジスタは、しきい電圧調節用Ｐ形不純物イオン１
０の注入後、ゲート５の下部にあるフィールド酸化膜２
の下部の活性領域Ａ’にＰ形不純物の欠乏層２０が形成
される。このような欠乏層２０はＮＭＯＳトランジスタ
の動作時にソース及びドレインの間に漏洩電流（ｌｅａ
ｋａｇｅ ｃｕｒｒｅｎｔ）を発生させて素子の電気的
特性を低下させる。However, the above-mentioned NMOS
The transistor is a threshold voltage adjusting P-type impurity ion 1
After the implantation of 0, the field oxide film 2 under the gate 5
A p-type impurity deficient layer 20 is formed in an active region A 'below. The depletion layer 20 has a leakage current between the source and the drain during operation of the NMOS transistor.
Kage current is generated to degrade the electrical characteristics of the device.
【００１０】従って、本発明の目的は、低いしきい電圧
を有するトランジスタにおいて、活性領域の不純物欠乏
による漏洩電流を防止することのできるＭＯＳトランジ
スタ及びその製造方法を提供することにある。It is therefore an object of the present invention to provide a MOS transistor having a low threshold voltage and capable of preventing a leakage current due to a lack of impurities in an active region, and a method of manufacturing the same.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、本発明による低いしきい電圧を有する半導体装置
は、所定の導電型の半導体基板と、基板上に形成された
フィールド絶縁膜と、フィールド絶縁膜によって前記基
板内に定められた活性領域と、フィールド絶縁膜を囲む
ように基板に形成された基板と同一の導電型の不純物領
域と、基板上に形成されたゲート絶縁膜と、ゲート絶縁
膜及びフィールド絶縁膜上に形成されたゲートパターン
とを含む。In order to achieve the above object, a semiconductor device having a low threshold voltage according to the present invention comprises a semiconductor substrate of a predetermined conductivity type, a field insulating film formed on the substrate, An active region defined in the substrate by the field insulating film, an impurity region of the same conductivity type as the substrate formed on the substrate so as to surround the field insulating film, a gate insulating film formed on the substrate, and a gate. An insulating film and a gate pattern formed on the field insulating film.
【００１２】また、上記目的を達成するために、本発明
による低いしきい電圧を有する半導体装置の製造方法
は、所定の導電型の半導体基板上にフィールド絶縁膜を
形成して活性領域を定められる工程と、基板に前記フィ
ールド絶縁膜の下部を囲むように基板と同一の導電型の
不純物領域を形成する工程と、基板にしきい電圧調節イ
オンを注入する工程と、基板上にゲート絶縁膜を形成す
る工程と、ゲート絶縁膜及びフィールド絶縁膜上にゲー
トパターンを形成する工程とを含む。According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a low threshold voltage, wherein a field insulating film is formed on a semiconductor substrate of a predetermined conductivity type to define an active region. Forming an impurity region of the same conductivity type as the substrate so as to surround a lower portion of the field insulating film in the substrate, implanting threshold voltage adjusting ions into the substrate, and forming a gate insulating film on the substrate And forming a gate pattern on the gate insulating film and the field insulating film.
【００１３】本発明によれば、ゲートの下部のフィール
ド絶縁膜の下部の活性領域が不純物領域まで拡張され
る。これにより、形不純物領域より不純物の濃度が相対
的に低い基板の活性領域で不純物の欠乏が防止される。According to the present invention, the active region below the field insulating film below the gate is extended to the impurity region. This prevents impurity deficiency in the active region of the substrate where the impurity concentration is relatively lower than that of the shaped impurity region.
【００１４】[0014]
【発明の実施の形態】以下、添付図面を参照して本発明
の実施例を説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００１５】図３は本発明による低いしきい電圧を有す
るＮＭＯＳトランジスタの平面図である。FIG. 3 is a plan view of an NMOS transistor having a low threshold voltage according to the present invention.
【００１６】図３に示すように、初期のＰ形基板（図示
せず）に低いしきい電圧を有するＮＭＯＳトランジスタ
の活性領域ＡＡが定められる。この際、活性領域ＡＡは
その中央部分の両側の所定部分が縦の方に突出した突出
部位ＡＡ’を有する。活性領域ＡＡの突出部位ＡＡ’と
所定部分が重なると共に、活性領域ＡＡから所定間隔を
おいて前記基板にＰウェル３３が形成される。活性領域
ＡＡの前記中央上部に突出部位ＡＡ’及びＰウェル３３
まで所定部分が拡張されたゲート３５が形成される。即
ち、活性領域ＡＡの所定部分がゲート３５の下部でＰウ
ェル３３に拡張されている。As shown in FIG. 3, an active region AA of an NMOS transistor having a low threshold voltage is defined on an initial P-type substrate (not shown). At this time, the active region AA has a protruding portion AA ′ in which predetermined portions on both sides of the central portion protrude vertically. A P-well 33 is formed in the substrate at a predetermined distance from the active region AA while a predetermined portion overlaps with the projecting portion AA ′ of the active region AA. The protruding portion AA ′ and the P well 33 are provided at the upper center of the active region AA
A gate 35 having a predetermined portion extended to the above is formed. That is, a predetermined portion of the active region AA is extended to the P well 33 below the gate 35.
【００１７】図４Ａ乃至図４Ｃは図３のIV−IV’線に沿
って切断された断面図であって、図４Ａ乃至図４Ｃを参
照して本発明の一実施例によるＮＭＯＳトランジスタの
製造方法を説明する。FIGS. 4A to 4C are cross-sectional views taken along the line IV-IV 'of FIG. 3. Referring to FIGS. 4A to 4C, a method of manufacturing an NMOS transistor according to an embodiment of the present invention will be described. Will be described.
【００１８】図４Ａに示すように、初期のＰ形半導体基
板３１上にフィールド酸化膜３２が形成されて低いしき
い電圧を有するＮＭＯＳトランジスタの活性領域ＡＡが
定められる。この時、フィールド酸化膜３２は従来のも
のより一定距離だけさらに離れて形成され、活性領域Ａ
Ａが図面に示すように、従来の活性領域Ａ，Ａ’より所
定領域だけ拡張されて定められる。そして、活性領域Ａ
Ａ，ＡＡ’上にスクリーン絶縁膜９０が形成される。As shown in FIG. 4A, a field oxide film 32 is formed on an initial P-type semiconductor substrate 31 to define an active region AA of an NMOS transistor having a low threshold voltage. At this time, the field oxide film 32 is formed further apart from the conventional one by a certain distance, and the active region A is formed.
As shown in the drawing, A is defined by extending a predetermined area from the conventional active areas A and A '. And the active region A
The screen insulating film 90 is formed on A and AA '.
【００１９】図４Ｂに示すように、フィールド酸化膜３
２を囲みつつ拡張された活性領域、即ち図３の突出部位
ＡＡ’を含むように基板にＰウェル３３が形成される。
その後、活性領域ＡＡ，ＡＡ’にしきい電圧調節用Ｐ形
不純物イオン１００、好ましくはＢイオンを約１０〜５
０ＫｅＶのエネルギーと５×１０11〜５×１０12ions／
cm2 の濃度でイオン注入するか、またはＢＦ2 イオンを
３０〜８０ＫｅＶのエネルギーと５×１０11〜５×１０
12ions／cm2 の濃度でイオン注入する。これによって調
節されたしきい電圧は約０．２〜０．４Ｖ程度になる。As shown in FIG. 4B, the field oxide film 3
A P-well 33 is formed in the substrate so as to include an extended active region surrounding the area 2, that is, the protruding portion AA ′ of FIG.
Thereafter, P-type impurity ions 100 for adjusting the threshold voltage, preferably B ions, are applied to the active regions AA and AA 'for about 10 to 5 times.
Energy of 0 KeV and 5 × 10 11 to 5 × 10 12 ions /
Ion implantation at a concentration of cm 2 or BF 2 ions at an energy of 30 to 80 KeV and 5 × 10 11 to 5 × 10
Ions are implanted at a concentration of 12 ions / cm 2 . The adjusted threshold voltage is about 0.2 to 0.4V.
【００２０】図４Ｃに示すように、スクリーン絶縁膜９
０が除去され、活性領域ＡＡ，ＡＡ’上にゲート絶縁膜
３４が形成される。そして、基板上部にゲート３５が形
成される。As shown in FIG. 4C, the screen insulating film 9
0 is removed, and a gate insulating film 34 is formed on the active regions AA and AA '. Then, a gate 35 is formed above the substrate.
【００２１】上記実施例によれば、低いしきい電圧を持
つＮＭＯＳトランジスタのゲート３５下部のフィールド
酸化膜３２下部の活性領域ＡＡがＰウェル３３まで拡張
される。これにより、Ｐウェル３３より相対的にＰ形不
純物の濃度が低い初期のＰ形基板３１の活性領域ＡＡで
Ｐ形不純物の欠乏が防止される。According to the above embodiment, the active region AA under the field oxide film 32 under the gate 35 of the NMOS transistor having a low threshold voltage is extended to the P well 33. As a result, deficiency of the P-type impurity in the active region AA of the P-type substrate 31 in which the concentration of the P-type impurity is relatively lower than that of the P-well 33 is prevented.
【００２２】図５Ａ及び図５Ｂは本発明の他の実施例に
よるＮＭＯＳトランジスタの断面図であって、断面方向
は図３のIV−IV’線に沿って切断された方向を示す。一
方、ここでは基板にＰウェルが形成された状態で、相対
的に低いしきい電圧を有するＮＭＯＳトランジスタの製
造方法を説明する。FIGS. 5A and 5B are cross-sectional views of an NMOS transistor according to another embodiment of the present invention, and the cross-sectional direction is a direction cut along line IV-IV ′ of FIG. On the other hand, a method of manufacturing an NMOS transistor having a relatively low threshold voltage in a state where a P well is formed in a substrate will be described.
【００２３】図５Ａに示すように、初期のＰ形半導体基
板５１のＮＭＯＳトランジスタ予定領域にＰ形不純物イ
オン、好ましくはＢイオンが約５０〜１５０ＫｅＶのエ
ネルギーと５×１０12〜５×１０13ions／cm2 の濃度で
イオン注入された後、拡散工程によってＰウェル５２が
形成される。これにより、ＮＭＯＳトランジスタのしき
い電圧は０．２〜０．４Ｖ程度になる。そして、Ｐウェ
ル５２上にフィールド酸化膜５３が形成されて活性領域
ＡＡが定められる。この時、フィールド酸化膜５２は従
来より一定距離だけさらに離れて形成され、活性領域Ａ
Ａが図面に示されたように、従来の活性領域Ａ，Ａ’よ
り図３の突出部位ＡＡ’だけ拡張されて定められる。そ
の後、活性領域ＡＡ，ＡＡ’上にスクリーン絶縁膜５４
が形成される。As shown in FIG. 5A, P-type impurity ions, preferably B ions, are added to the region where the NMOS transistor is to be formed in the initial P-type semiconductor substrate 51 at an energy of about 50 to 150 KeV and 5 × 10 12 to 5 × 10 13 ions. After ion implantation at a concentration of / cm 2, a P well 52 is formed by a diffusion process. As a result, the threshold voltage of the NMOS transistor becomes about 0.2 to 0.4V. Then, a field oxide film 53 is formed on the P well 52 to define an active region AA. At this time, the field oxide film 52 is formed further apart from the conventional device by a certain distance, and
As shown in the drawing, A is defined by extending from the conventional active regions A and A 'by the protruding portion AA' in FIG. Thereafter, the screen insulating film 54 is formed on the active regions AA and AA '.
Is formed.
【００２４】図５Ｂに示すように、フィールド酸化膜５
３を囲みつつ活性領域ＡＡの突出部位ＡＡ’を含むよう
にＰ形不純物領域５５ａ，５５ｂが形成される。この
際、Ｐ形不純物領域５５ａ，５５ｂはＢイオンが約６０
〜１５０ＫｅＶのエネルギーと１×１０12〜１×１０13
ions／cm2 の濃度でイオン注入されて形成される。この
時、Ｐ形不純物領域５５ａ，５５ｂは活性領域ＡＡのソ
ース及びドレイン予定領域（図３参照）には形成されな
い。即ち、活性領域ＡＡの突出部位ＡＡ’はＰ形不純物
領域５５ａ，５５ｂからなる。そして、スクリーン絶縁
膜５４が除去され、活性領域ＡＡ，ＡＡ’上にゲート絶
縁膜５６が形成される。その後、基板上にゲート５７が
形成される。As shown in FIG. 5B, the field oxide film 5
P-type impurity regions 55a and 55b are formed so as to include a protruding portion AA ′ of active region AA while surrounding 3. At this time, the P-type impurity regions 55a and 55b
Energy of ~ 150 KeV and 1 × 10 12 -1 × 10 13
It is formed by ion implantation at a concentration of ions / cm 2 . At this time, the P-type impurity regions 55a and 55b are not formed in the planned source and drain regions (see FIG. 3) of the active region AA. That is, the protruding portion AA 'of the active region AA includes the P-type impurity regions 55a and 55b. Then, the screen insulating film 54 is removed, and a gate insulating film 56 is formed on the active regions AA and AA '. Thereafter, a gate 57 is formed on the substrate.
【００２５】上記実施例によれば、Ｐウェルが形成され
た状態で、相対的に低いしきい電圧を有するＮＭＯＳト
ランジスタのゲート５７下部のフィールド酸化膜５３の
下部の活性領域ＡＡがＰ形不純物領域まで拡張される。
これにより、Ｐ形不純物領域よりＰ形不純物の濃度が相
対的に低いＰウェルの活性領域ＡＡでＰ形不純物の欠乏
が防止される。According to the above embodiment, when the P well is formed, the active region AA under the field oxide film 53 under the gate 57 of the NMOS transistor having a relatively low threshold voltage is replaced with the P type impurity region. Extended to
This prevents P-type impurity deficiency in the active region AA of the P-well where the concentration of the P-type impurity is relatively lower than that of the P-type impurity region.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によれば、
低いしきい電圧を有するトランジスタのゲート下部にあ
る活性領域で生じる不純物の欠乏が防止される。これに
より、トランジスタの動作時にソース及びドレインの間
で発生する漏洩電流が防止されることにより、低いしき
い電圧を有するトランジスタの特性が向上する。As described above, according to the present invention,
Impurity depletion, which occurs in the active region below the gate of a transistor having a low threshold voltage, is prevented. Accordingly, leakage current generated between the source and the drain during operation of the transistor is prevented, so that characteristics of the transistor having a low threshold voltage are improved.
【００２７】尚、本発明は前記実施例に限らず、本発明
の技術的な要旨から外れない範囲内で多様に変形させて
実施することができる。It should be noted that the present invention is not limited to the above-described embodiment, but can be carried out in various modifications without departing from the technical scope of the present invention.
【図１】従来の低いしきい電圧を有するＮＭＯＳトラン
ジスタの平面図である。FIG. 1 is a plan view of a conventional NMOS transistor having a low threshold voltage.
【図２】従来の低いしきい電圧を有するＮＭＯＳトラン
ジスタの断面図である。FIG. 2 is a cross-sectional view of a conventional NMOS transistor having a low threshold voltage.
【図３】本発明による低いしきい電圧を有するＮＭＯＳ
トランジスタの平面図である。FIG. 3 shows a low threshold voltage NMOS according to the present invention.
FIG. 3 is a plan view of a transistor.
【図４】（Ａ）〜（Ｃ）は、本発明の一実施例による低
いしきい電圧を有するＮＭＯＳトランジスタの製造方法
を説明するための断面図である。FIGS. 4A to 4C are cross-sectional views illustrating a method for manufacturing an NMOS transistor having a low threshold voltage according to an embodiment of the present invention;
【図５】（Ａ）及び（Ｂ）は、本発明の他の実施例によ
る低いしきい電圧を有するＮＭＯＳトランジスタの製造
方法を説明するための断面図である。FIGS. 5A and 5B are cross-sectional views illustrating a method of manufacturing an NMOS transistor having a low threshold voltage according to another embodiment of the present invention.
Ａ，Ａ’，ＡＡ，ＡＡ’ 活性領域 ３１，５１ Ｐ形半導体基板 ３２，５３ フィールド酸化膜 ３３，５２ Ｐウェル ３４，５６ ゲート絶縁膜 ３５，５７ ゲート ９０，５４ スクリーン絶縁膜 ５５ａ，５５ｂ Ｐ形不純物領域 １００ しきい電圧調節用Ｐ形不純物イオン A, A ', AA, AA' Active region 31, 51 P-type semiconductor substrate 32, 53 Field oxide film 33, 52 P well 34, 56 Gate insulating film 35, 57 Gate 90, 54 Screen insulating film 55a, 55b P-type Impurity region 100 P-type impurity ion for threshold voltage adjustment
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成９年９月１日[Submission date] September 1, 1997
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２３[Correction target item name] 0023
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２３】図５Ａに示すように、初期のＰ形半導体基
板５１のＮＭＯＳトランジスタ予定領域にＰ形不純物イ
オン、好ましくはＢイオンが約５０〜１５０ＫｅＶのエ
ネルギーと５×１０１２〜５×１０１３ｉｏｎｓ／ｃｍ
２の濃度でイオン注入された後、拡散工程によってＰウ
ェル５２が形成される。これにより、ＮＭＯＳトランジ
スタのしきい電圧は０．２〜０．４Ｖ程度になる。そし
て、Ｐウェル５２上にフィールド酸化膜５２が形成され
て活性領域ＡＡが定められる。この時、フィールド酸化
膜５２は従来より一定距離だけさらに離れて形成され、
活性領域ＡＡが図面に示されたように、従来の活性領域
Ａ，Ａ’より図３の突出部位ＡＡ’だけ拡張されて定め
られる。その後、活性領域ＡＡ，ＡＡ’上にスクリーン
絶縁膜５４が形成される。As shown in FIG. 5A, P-type impurity ions, preferably B ions, are added to the region where the NMOS transistor is to be formed in the initial P-type semiconductor substrate 51 at an energy of about 50 to 150 KeV and 5 × 10 12 to 5 × 10 13 ions. / Cm
After ion implantation at a concentration of 2, a P-well 52 is formed by a diffusion process. As a result, the threshold voltage of the NMOS transistor becomes about 0.2 to 0.4V. Then, a field oxide film 52 is formed on P well 52 to define an active region AA. At this time, the field oxide film 52 is formed further apart from the conventional device by a certain distance.
As shown in the drawing, the active region AA is defined by extending from the conventional active regions A and A 'by the protruding portion AA' in FIG. Thereafter, a screen insulating film 54 is formed on the active regions AA and AA '.
Claims (8)
て、 所定の導電型の半導体基板と、 前記基板上に形成されたフィールド絶縁膜と、 前記フィールド絶縁膜によって前記基板内に定められた
活性領域と、 前記フィールド絶縁膜を囲むように前記基板内に形成さ
れた前記基板と同一の導電型の不純物領域と、 前記基板上に形成されたゲート絶縁膜と、 前記ゲート絶縁膜及びフィールド絶縁膜上に形成された
ゲートパターンとを含むことを特徴とする半導体装置。1. A semiconductor device having a low threshold voltage, comprising: a semiconductor substrate having a predetermined conductivity type; a field insulating film formed on the substrate; and an active region defined in the substrate by the field insulating film. An impurity region of the same conductivity type as the substrate formed in the substrate so as to surround the field insulating film; a gate insulating film formed on the substrate; And a gate pattern formed on the semiconductor device.
方法において、 所定の導電型の半導体基板上にフィールド絶縁膜を形成
して活性領域を定める工程と、 前記基板内に前記フィールド絶縁膜の下部を囲むように
前記基板と同一の導電型の不純物領域を形成する工程
と、 前記基板内にしきい電圧調節イオンを注入する工程と、 前記基板上にゲート絶縁膜を形成する工程と、 前記ゲート絶縁膜及びフィールド絶縁膜上にゲートパタ
ーンを形成する工程とを含むことを特徴とする半導体装
置の製造方法。2. A method of manufacturing a semiconductor device having a low threshold voltage, comprising: forming a field insulating film on a semiconductor substrate of a predetermined conductivity type to define an active region; Forming an impurity region of the same conductivity type as that of the substrate so as to surround the lower part; implanting a threshold voltage adjusting ion into the substrate; forming a gate insulating film on the substrate; Forming a gate pattern on the insulating film and the field insulating film.
れていない初期の基板であることを特徴とする請求項２
記載の半導体装置の製造方法。3. The semiconductor substrate according to claim 2, wherein the semiconductor substrate is an initial substrate that is not doped with impurities.
The manufacturing method of the semiconductor device described in the above.
程はＢイオンを約１０〜５０ＫｅＶのエネルギーと５×
１０11〜５×１０12ions／cm2 の濃度でイオン注入する
ことを特徴とする請求項３記載の半導体装置の製造方
法。4. The step of implanting the threshold voltage adjusting ions comprises implanting B ions with an energy of about 10 to 50 KeV and 5 ×
4. The method according to claim 3, wherein ions are implanted at a concentration of 10 11 to 5 × 10 12 ions / cm 2 .
程はＢＦ2 を３０〜８０ｋｅＶのエネルギーと５×１０
11〜５×１０12ions／cm2 の濃度でイオン注入すること
を特徴とする請求項３記載の半導体装置の製造方法。5. The step of implanting the threshold voltage adjusting ions comprises the step of implanting BF 2 with energy of 30 to 80 keV and 5 × 10 5
4. The method according to claim 3, wherein ions are implanted at a concentration of 11 to 5 * 10 < 12 > ions / cm < 2 >.
板であることを特徴とする請求項２記載の半導体装置の
製造方法。6. The method according to claim 2, wherein the semiconductor substrate is a substrate on which a well is formed.
ｅＶのエネルギーと５×１０12〜５×１０13ions／cm2
の濃度でイオン注入して形成することを特徴とする請求
項６記載の半導体装置の製造方法。7. The well according to claim 5, wherein the B ion is 50 to 150K.
eV energy and 5 × 10 12 to 5 × 10 13 ions / cm 2
7. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is formed by ion implantation at a concentration of.
０ＫｅＶのエネルギーと１×１０12〜１×１０13ions／
cm2 でイオン注入して形成することを特徴とする請求項
６記載の半導体装置の製造方法。8. The semiconductor device according to claim 1, wherein the impurity region contains 60 to 15 B ions.
Energy of 0 KeV and 1 × 10 12 to 1 × 10 13 ions /
7. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is formed by ion-implantation at cm 2 .
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960026296A KR100233558B1 (en) | 1996-06-29 | 1996-06-29 | Manufacturing method of a semiconductor device |
| KR1996P26296 | 1996-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1070272A true JPH1070272A (en) | 1998-03-10 |
Family
ID=19465048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9183142A Pending JPH1070272A (en) | 1996-06-29 | 1997-06-24 | Semiconductor device and fabrication thereof |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH1070272A (en) |
| KR (1) | KR100233558B1 (en) |
| CN (1) | CN1136613C (en) |
| DE (1) | DE19727491A1 (en) |
| GB (1) | GB2314973B (en) |
| TW (1) | TW416113B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007523481A (en) * | 2004-02-17 | 2007-08-16 | シリコン・スペース・テクノロジー・コーポレイション | Embedded guard ring, radiation-resistant separation structure and manufacturing method thereof |
| WO2007108104A1 (en) * | 2006-03-20 | 2007-09-27 | Fujitsu Limited | Semiconductor device and its fabrication process |
| JP2009267027A (en) * | 2008-04-24 | 2009-11-12 | Seiko Epson Corp | Semiconductor device, and method for manufacturing thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8278719B2 (en) | 2005-10-14 | 2012-10-02 | Silicon Space Technology Corp. | Radiation hardened isolation structures and fabrication methods |
| JP4288355B2 (en) * | 2006-01-31 | 2009-07-01 | 国立大学法人北陸先端科学技術大学院大学 | Ternary logic function circuit |
| US10038058B2 (en) | 2016-05-07 | 2018-07-31 | Silicon Space Technology Corporation | FinFET device structure and method for forming same |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2084794B (en) * | 1980-10-03 | 1984-07-25 | Philips Electronic Associated | Methods of manufacturing insulated gate field effect transistors |
| JPH0693494B2 (en) * | 1984-03-16 | 1994-11-16 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
| JPS61292358A (en) * | 1985-06-19 | 1986-12-23 | Fujitsu Ltd | Manufacture of mis field effect transistor |
| JPS62200767A (en) * | 1986-02-28 | 1987-09-04 | Toshiba Corp | Mos-type semiconductor device |
| JPS6425438A (en) * | 1987-07-21 | 1989-01-27 | Sony Corp | Manufacture of semiconductor device |
| JPH0235778A (en) * | 1988-07-26 | 1990-02-06 | Seiko Epson Corp | Semiconductor device |
| US5525823A (en) * | 1992-05-08 | 1996-06-11 | Sgs-Thomson Microelectronics, Inc. | Manufacture of CMOS devices |
| US5396096A (en) * | 1992-10-07 | 1995-03-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US5432107A (en) * | 1992-11-04 | 1995-07-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor fabricating method forming channel stopper with diagonally implanted ions |
| JPH07135317A (en) * | 1993-04-22 | 1995-05-23 | Texas Instr Inc <Ti> | Self-aligned silicide gate |
-
1996
- 1996-06-29 KR KR1019960026296A patent/KR100233558B1/en not_active IP Right Cessation
-
1997
- 1997-06-17 TW TW086108423A patent/TW416113B/en not_active IP Right Cessation
- 1997-06-24 JP JP9183142A patent/JPH1070272A/en active Pending
- 1997-06-26 GB GB9713545A patent/GB2314973B/en not_active Expired - Fee Related
- 1997-06-27 DE DE19727491A patent/DE19727491A1/en not_active Ceased
- 1997-06-28 CN CNB971138710A patent/CN1136613C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007523481A (en) * | 2004-02-17 | 2007-08-16 | シリコン・スペース・テクノロジー・コーポレイション | Embedded guard ring, radiation-resistant separation structure and manufacturing method thereof |
| WO2007108104A1 (en) * | 2006-03-20 | 2007-09-27 | Fujitsu Limited | Semiconductor device and its fabrication process |
| JP2009267027A (en) * | 2008-04-24 | 2009-11-12 | Seiko Epson Corp | Semiconductor device, and method for manufacturing thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR980006490A (en) | 1998-03-30 |
| GB9713545D0 (en) | 1997-09-03 |
| CN1173739A (en) | 1998-02-18 |
| DE19727491A1 (en) | 1998-01-02 |
| GB2314973A (en) | 1998-01-14 |
| KR100233558B1 (en) | 1999-12-01 |
| TW416113B (en) | 2000-12-21 |
| GB2314973B (en) | 2001-09-19 |
| CN1136613C (en) | 2004-01-28 |
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