KR950015715A - 반도체 장치의 소자 분리막 형성방법 - Google Patents

반도체 장치의 소자 분리막 형성방법 Download PDF

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Publication number
KR950015715A
KR950015715A KR1019930024975A KR930024975A KR950015715A KR 950015715 A KR950015715 A KR 950015715A KR 1019930024975 A KR1019930024975 A KR 1019930024975A KR 930024975 A KR930024975 A KR 930024975A KR 950015715 A KR950015715 A KR 950015715A
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KR
South Korea
Prior art keywords
forming
isolation film
silicon nitride
oxide film
film
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KR1019930024975A
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English (en)
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KR100187678B1 (ko
Inventor
한충수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930024975A priority Critical patent/KR100187678B1/ko
Priority to JP6288262A priority patent/JPH07321194A/ja
Priority to US08/346,929 priority patent/US5512509A/en
Priority to DE4441706A priority patent/DE4441706A1/de
Publication of KR950015715A publication Critical patent/KR950015715A/ko
Application granted granted Critical
Publication of KR100187678B1 publication Critical patent/KR100187678B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 장치의 소자분리막 형성방법에 관한 것으로, 소자분리막을 형성하기 위한 트렌치(trench)의 측벽에 실리콘 질화막과 다결정 실리콘을 형성한 수 필드 산화 공정을 실시하므로 버즈 비크(birds beak) 및 스트레스(stress)를 줄일 수 있는 반도체 장치의 소자 분리막 형성 방법에 관해 기술된다.

Description

반도체 장치의 소자 분리막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2e도는 본 발명에 따라 반도체 장치의 소자 분리막 형성단계를도시한 단면도.

Claims (1)

  1. 반도체 장치의 소자 분리막 형성방법에 있어서, 반도체 기판(1)상에 패드 산화막 및 제1실리콘 질화막(2 및 10)을 형성한 다음 포토레지스트(9)를도포하고 패턴화하는 단계와, 상기 단계로부터 상기 제1실리콘 질화막, 패드 산화막 및 반도체 기판(10, 2 및 1)을 식각하여 트렌치(4)를 형성하고 상기 포토레지스트(9)를 제거한 다음 희생 산화막(5)을 형성하는 단계와, 상기 단계로부터 제2실리콘 질화막 및 다결정 실리콘(11 및 12)을 증착한 상태에서 상기 다결정 실리콘(12)을 스페이서 에치하여 다결정 실리콘 스페이서(12A)를 형성하는 단계와, 상기 단계로부터 상기 다결정 실리콘 스페이서(12A)를 마스크로 하여 상기 트렌치(4) 저부의 제2실리콘 질화막(11)을 식각하고 필드 산화공정을 실시하는 단계와, 상기 단계로부터 상기 반도체 기판(1) 상부의 패드 산화막(2), 제1 및 제 실리콘 질화막(10 및 11)을 제거하여 필드 산화막(8)을 완성하는 단계로 이루어진 것을 특징으로 하는 반도체 장치의 소자 분리막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930024975A 1993-11-23 1993-11-23 반도체 장치의 소자 분리막 형성방법 KR100187678B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019930024975A KR100187678B1 (ko) 1993-11-23 1993-11-23 반도체 장치의 소자 분리막 형성방법
JP6288262A JPH07321194A (ja) 1993-11-23 1994-11-22 半導体装置の素子分離層の形成方法
US08/346,929 US5512509A (en) 1993-11-23 1994-11-23 Method for forming an isolation layer in a semiconductor device
DE4441706A DE4441706A1 (de) 1993-11-23 1994-11-23 Verfahren zur Bildung einer Isolationsschicht für eine Halbleitervorrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930024975A KR100187678B1 (ko) 1993-11-23 1993-11-23 반도체 장치의 소자 분리막 형성방법

Publications (2)

Publication Number Publication Date
KR950015715A true KR950015715A (ko) 1995-06-17
KR100187678B1 KR100187678B1 (ko) 1999-06-01

Family

ID=19368707

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930024975A KR100187678B1 (ko) 1993-11-23 1993-11-23 반도체 장치의 소자 분리막 형성방법

Country Status (4)

Country Link
US (1) US5512509A (ko)
JP (1) JPH07321194A (ko)
KR (1) KR100187678B1 (ko)
DE (1) DE4441706A1 (ko)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866467A (en) * 1995-12-08 1999-02-02 Advanced Micro Devices, Inc. Method of improving oxide isolation in a semiconductor device
US5972776A (en) * 1995-12-22 1999-10-26 Stmicroelectronics, Inc. Method of forming a planar isolation structure in an integrated circuit
TW309647B (ko) * 1995-12-30 1997-07-01 Hyundai Electronics Ind
US5658822A (en) * 1996-03-29 1997-08-19 Vanguard International Semiconductor Corporation Locos method with double polysilicon/silicon nitride spacer
US5824594A (en) * 1996-04-29 1998-10-20 Samsung Electronics Co., Ltd. Integrated circuit device isolating methods including silicon spacers and oxidation barrier films
US6121087A (en) * 1996-06-18 2000-09-19 Conexant Systems, Inc. Integrated circuit device with embedded flash memory and method for manufacturing same
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US5753962A (en) * 1996-09-16 1998-05-19 Micron Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US5976950A (en) * 1997-11-13 1999-11-02 National Semiconductor Corporation Polysilicon coated swami (sidewall masked isolation)
KR100475050B1 (ko) * 1998-09-24 2005-07-05 삼성전자주식회사 스페이서로보호되는박막의질화막라이너를갖는트렌치소자분리방법및구조
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
US6417093B1 (en) 2000-10-31 2002-07-09 Lsi Logic Corporation Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
US6586814B1 (en) 2000-12-11 2003-07-01 Lsi Logic Corporation Etch resistant shallow trench isolation in a semiconductor wafer
US6617251B1 (en) 2001-06-19 2003-09-09 Lsi Logic Corporation Method of shallow trench isolation formation and planarization
US7007900B2 (en) * 2002-10-01 2006-03-07 Andrew Corporation Cable hanger
KR100980055B1 (ko) 2003-06-30 2010-09-03 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
US20070224772A1 (en) * 2006-03-21 2007-09-27 Freescale Semiconductor, Inc. Method for forming a stressor structure
KR100824205B1 (ko) * 2006-12-26 2008-04-21 매그나칩 반도체 유한회사 Dmos 트랜지스터 및 그 제조방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992547A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd アイソレ−シヨン方法
JPS6214439A (ja) * 1985-07-12 1987-01-23 Nec Corp 半導体装置の製造方法
JPS6324635A (ja) * 1986-07-17 1988-02-02 Toshiba Corp 半導体装置の製造方法
JPS63258040A (ja) * 1987-04-15 1988-10-25 Nec Corp 素子分離領域の形成方法
JP2747563B2 (ja) * 1987-06-15 1998-05-06 ヒュンダイ エレクトロニクス アメリカ 半導体のフイールド酸化物形成方法
JPH0199234A (ja) * 1987-10-13 1989-04-18 Matsushita Electric Ind Co Ltd 分離領域形成方法
JPH0461123A (ja) * 1990-06-22 1992-02-27 Nec Corp 半導体装置の素子分離方法
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture

Also Published As

Publication number Publication date
KR100187678B1 (ko) 1999-06-01
US5512509A (en) 1996-04-30
JPH07321194A (ja) 1995-12-08
DE4441706A1 (de) 1995-05-24

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