KR970023988A - 반도체장치의 소자격리방법(An isolation method of semiconductor device) - Google Patents

반도체장치의 소자격리방법(An isolation method of semiconductor device) Download PDF

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Publication number
KR970023988A
KR970023988A KR1019950036191A KR19950036191A KR970023988A KR 970023988 A KR970023988 A KR 970023988A KR 1019950036191 A KR1019950036191 A KR 1019950036191A KR 19950036191 A KR19950036191 A KR 19950036191A KR 970023988 A KR970023988 A KR 970023988A
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South Korea
Prior art keywords
isolation region
device isolation
film
forming
semiconductor
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KR1019950036191A
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English (en)
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KR100196423B1 (ko
Inventor
안중일
이재일
박준일
안응용
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김광호
삼성전자 주식회사
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Priority to KR1019950036191A priority Critical patent/KR100196423B1/ko
Publication of KR970023988A publication Critical patent/KR970023988A/ko
Application granted granted Critical
Publication of KR100196423B1 publication Critical patent/KR100196423B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

반도체상의 소자격리영역을 형성함에 있어서, 실리콘 기판상에 SixOyNz막, 질화막, 포토 레지스트막을 차례로 형성하고, 포토 레지스트막을 패터닝하여 소자격리영역을 한정한 후, 소자격리영역상의 질화막과 SixOyNz막을 선택적으로 식각하여 제거한다. 상기와 같은 구조물상에 습식 산화 공정을 실시하면, 소자격리영역으로 필드 산화막이 형성되고, 종래의 소자격리영역상의 문제점이었던 소자격리영역상의 버즈비크 현상이 현저하게 줄어들고, 상대적으로 소자 형성 영역이 넓어짊에 따라, 반도체 소자의 안정화를 기할 수 있으며, 반도체 수율의 향상에도 기여하게 된다.

Description

반도체장치의 소자격리방법(An isolation method of semiconductor device)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도내지 제2D도는 본 발명에 방법에 의하여 반도체 소자를 격리하기 위한 필드 산화막을 형성하는 공정도이다.

Claims (1)

  1. 웨이퍼상의 소자격리영역을 형성함에 있어서, 실리콘 기판상에 SixOyNz막, 질화막, 포토 레지스트막을 차례로 형성하는 공정과, 상기 포토 레지스트막을 패터닝하여 소자 격리영역을 한정하는 공정과, 상기 소자격리영역 상의 질화막, SixOyNz막을 선택적인 식각 공정에 의해 차례로 제거하는 공정과, 상기 소자 격리영역상에 습식산화방법을 이용하여 필드 산화시켜서 필드 산화막을 소자격리영역상에 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 소자격리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950036191A 1995-10-19 1995-10-19 반도체장치의 소자격리방법 KR100196423B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950036191A KR100196423B1 (ko) 1995-10-19 1995-10-19 반도체장치의 소자격리방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036191A KR100196423B1 (ko) 1995-10-19 1995-10-19 반도체장치의 소자격리방법

Publications (2)

Publication Number Publication Date
KR970023988A true KR970023988A (ko) 1997-05-30
KR100196423B1 KR100196423B1 (ko) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950036191A KR100196423B1 (ko) 1995-10-19 1995-10-19 반도체장치의 소자격리방법

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KR100196423B1 (ko) 1999-06-15

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