KR940022765A - 반도체 장치의 상호 접속구조 및 상호접속 방법 - Google Patents

반도체 장치의 상호 접속구조 및 상호접속 방법 Download PDF

Info

Publication number
KR940022765A
KR940022765A KR1019940004651A KR19940004651A KR940022765A KR 940022765 A KR940022765 A KR 940022765A KR 1019940004651 A KR1019940004651 A KR 1019940004651A KR 19940004651 A KR19940004651 A KR 19940004651A KR 940022765 A KR940022765 A KR 940022765A
Authority
KR
South Korea
Prior art keywords
electronic component
core member
solder
interconnect structure
pad
Prior art date
Application number
KR1019940004651A
Other languages
English (en)
Other versions
KR0153212B1 (ko
Inventor
겐지 쯔까모또
Original Assignee
세끼모또 다다히로
니뽄 덴끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세끼모또 다다히로, 니뽄 덴끼 가부시끼가이샤 filed Critical 세끼모또 다다히로
Publication of KR940022765A publication Critical patent/KR940022765A/ko
Application granted granted Critical
Publication of KR0153212B1 publication Critical patent/KR0153212B1/ko

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/1031Surface mounted metallic connector elements
    • H05K2201/10318Surface mounted metallic pins
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

본 발명에 따른 상호접속 구조는 구조를 단순화하여 제조가 쉽고 솔더 범프에 발생되는 응력을 최소화 한다. 반도체 칩의 패드와 기판의 패드는 솔더 범프에 의해 서로 접속된다. 상기 솔더 범프는 모래시계 형태이다. 금속 코어부재는 솔더 범프내에 각각 제공되고, 상기 코어부재는 원형 바닥부와 원형핀부로 구성되며, 또한 상기 코어는 반도체 칩의 패드에 땜납된다.

Description

반도체 장치의 상호 접속구조 및 상호접속 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 전자부품용 상호접속 구조도.
제2a도 내지 제2c도는 코어부재(4)의 구조 상세도.

Claims (16)

  1. 제1전자 부품을 제2전자부품에 접속시키기 위한 솔더 범프와 상기 솔더 범프에 제공된 코어부재를 각각 포함하는 것을 특징으로 하는 전자부품용 상호접속 구조.
  2. 제1항에 있어서, 상기 각각의 솔더 범프는 모래시계 형태인 것을 특징으로 하는 전자부품용 상호접속 구조.
  3. 제1항에 있어서, 상기 제1전자부품은 LSI 베어칩을 포함하고, 제2전자부품은 기판을 포함하는 것을 특징으로 하는 전자부품용 상호접속 구조.
  4. 제3항에 있어서, 상기 코어부재는 LSI 베어칩상에 제공되는 것을 특징으로 하는 전자부품용 상호접속 구조.
  5. 제3항에 있어서, 상기 코어부재는 기판상에 제공되는 것을 특징으로 하는 전자부품용 상호접속 구조.
  6. 제1항에 있어서, 상기 코어부재는 각각 핀 부분을 갖는 것을 특징으로 하는 전자부품용 상호접속 구조.
  7. 제6항에 있어서, 상기 코어부재의 핀 부분은 각각 정확히 위치 지정되는 것을 특징으로 하는 전자부품용 상호접속 구조.
  8. 제6항에 있어서, 상기 코어 부재의 핀 부분은 각각 타원형의 단면을 갖는 것을 특징으로 하는 전자부품용 상호접속 구조.
  9. 제6항에 있어서, 상기 코어 부재의 핀 부부은 상기 핀 부분의 상단부로부터 연장된 각각의 중심홀을 갖는 것을 특징으로 하는 전자부품용 상호접속 구조.
  10. 제6항에 있어서, 상기 각각의 코어부재는 다수의 핀 부분을 갖는 것을 특징으로 하는 전자부품용 상호접속 구조.
  11. 상기 제1전자부품의 각각의 패드상에 코어 부재를 장착하는 제1단계와, 상기 제2전자 부품의 패드를 예정된 솔더 페이스트 양으로 피복하는 제2단계와, 상기 코어 부재를 제2전자 부품의 패드상에 있는 솔더 페이스트내로 각각 삽입하는 제3단계 및, 상기 솔더 페이스트를 가열 용융시킨 후 솔더 범프를 형성하기 위해 솔더 페이스트를 냉각시키는 제4단계를 포함하는 것을 특징으로 하는 제1 및 제2전자부품의 상호접속 방법.
  12. 제11항에 있어서, 상기 제2전자부품의 각 패드상의 솔더 패이스트 양은 상기 솔더 패이스트가 제4단계에서 용융될 때 그 표면 장력에 의해 모래시계 형태를 제공하도록 선택되는 것을 특징으로 하는 제1 및 제2전자부품의 상호접속 방법.
  13. 상기 코어부재를 제1전자부품의 각 패드상에 장착하는 제1단계와, 환형 솔더를 상기 코어 부재상에 각각 끼우는 제2단계와, 상기 코어 부재가 제2전자부품의 패드와 각각 배열되도록 상기 제1전자부품을 제2전자 부품상에 위치시키는 제3단계 및, 상기 솔더링을 가열 및 용융시킨 다음 솔더 범프를 형성하도록 냉각시키는 제4단계를 포함하는 것을 특징으로 하는 제1 및 제2전자부품의 상호접속 방법.
  14. 제13항에 있어서, 각각의 솔더링을 형성하는 솔더양은 상기 솔더링이 제4단계에서 용융될 때 그 표면장력에 의해 모래시계 형태를 제공하도록 선택되는 것을 특징으로 하는 제1 및 제2전자부품의 상호접속 방법.
  15. LSI 베어칩의 패드상에 장착된 코어부재와 LSI 베어칩을 포함하는 것을 특징으로 하는 반도체 장치.
  16. 제15항에 있어서, 솔더량은 상기 각각의 코어부재에 부착되고, 상기 솔더양은 상기 솔더가 재유동시 모래시계 형태를 제공하도록 선택되는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940004651A 1993-03-10 1994-03-10 반도체 장치의 상호 접속 구조 및 상호 접속 방법 KR0153212B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5049172A JP2716336B2 (ja) 1993-03-10 1993-03-10 集積回路装置
JP93-49172 1993-03-11

Publications (2)

Publication Number Publication Date
KR940022765A true KR940022765A (ko) 1994-10-21
KR0153212B1 KR0153212B1 (ko) 1998-12-01

Family

ID=12823654

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940004651A KR0153212B1 (ko) 1993-03-10 1994-03-10 반도체 장치의 상호 접속 구조 및 상호 접속 방법

Country Status (7)

Country Link
US (1) US5640052A (ko)
EP (1) EP0615283B1 (ko)
JP (1) JP2716336B2 (ko)
KR (1) KR0153212B1 (ko)
AU (1) AU675273B2 (ko)
CA (1) CA2118649C (ko)
DE (1) DE69428819T2 (ko)

Families Citing this family (137)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US6008071A (en) * 1995-09-20 1999-12-28 Fujitsu Limited Method of forming solder bumps onto an integrated circuit device
US5736790A (en) * 1995-09-21 1998-04-07 Kabushiki Kaisha Toshiba Semiconductor chip, package and semiconductor device
US5829124A (en) * 1995-12-29 1998-11-03 International Business Machines Corporation Method for forming metallized patterns on the top surface of a printed circuit board
EP0791960A3 (en) * 1996-02-23 1998-02-18 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having protruding contacts and method for making the same
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JP2751912B2 (ja) * 1996-03-28 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
US6027791A (en) * 1996-09-30 2000-02-22 Kyocera Corporation Structure for mounting a wiring board
US5841198A (en) * 1997-04-21 1998-11-24 Lsi Logic Corporation Ball grid array package employing solid core solder balls
EP1009202B1 (en) 1997-06-04 2007-10-17 Ibiden Co., Ltd. Soldering member for printed wiring boards
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6013877A (en) * 1998-03-12 2000-01-11 Lucent Technologies Inc. Solder bonding printed circuit boards
US6023029A (en) * 1998-03-19 2000-02-08 International Business Machines Corporation Use of blind vias for soldered interconnections between substrates and printed wiring boards
JPH11340265A (ja) * 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法
WO2000016279A1 (en) * 1998-09-11 2000-03-23 Motorola Inc. Radio frequency identification tag circuit chip having printed interconnection pads
US6354850B1 (en) 1998-12-15 2002-03-12 Fci Americas Technology, Inc. Electrical connector with feature for limiting the effects of coefficient of thermal expansion differential
US6583354B2 (en) * 1999-04-27 2003-06-24 International Business Machines Corporation Method of reforming reformable members of an electronic package and the resultant electronic package
US6225206B1 (en) * 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
US6297562B1 (en) * 1999-09-20 2001-10-02 Telefonaktieboalget Lm Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
US6281041B1 (en) 1999-11-30 2001-08-28 Aptos Corporation Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball
US6430058B1 (en) 1999-12-02 2002-08-06 Intel Corporation Integrated circuit package
US6413849B1 (en) 1999-12-28 2002-07-02 Intel Corporation Integrated circuit package with surface mounted pins on an organic substrate and method of fabrication therefor
US6469394B1 (en) 2000-01-31 2002-10-22 Fujitsu Limited Conductive interconnect structures and methods for forming conductive interconnect structures
US6448171B1 (en) 2000-05-05 2002-09-10 Aptos Corporation Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
US6610591B1 (en) 2000-08-25 2003-08-26 Micron Technology, Inc. Methods of ball grid array
JP3735526B2 (ja) * 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
US6750396B2 (en) 2000-12-15 2004-06-15 Di/Dt, Inc. I-channel surface-mount connector
US6543674B2 (en) 2001-02-06 2003-04-08 Fujitsu Limited Multilayer interconnection and method
US6550666B2 (en) * 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US7138583B2 (en) * 2002-05-08 2006-11-21 Sandisk Corporation Method and apparatus for maintaining a separation between contacts
JP2004014854A (ja) * 2002-06-07 2004-01-15 Shinko Electric Ind Co Ltd 半導体装置
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
CN2652088Y (zh) * 2002-09-20 2004-10-27 日本特殊陶业株式会社 由树脂制成的带有插脚的电路板
US7015869B2 (en) * 2002-11-18 2006-03-21 Visteon Global Technologies, Inc. High frequency antenna disposed on the surface of a three dimensional substrate
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
KR100568006B1 (ko) * 2003-12-12 2006-04-07 삼성전자주식회사 플립 칩 패키지의 오목형 솔더 범프 구조 형성 방법
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US20050148111A1 (en) * 2003-12-30 2005-07-07 Texas Instruments Incorporated Method and system for producing resilient solder joints
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
US20060055032A1 (en) * 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
JP4891556B2 (ja) * 2005-03-24 2012-03-07 株式会社東芝 半導体装置の製造方法
US7667473B1 (en) * 2005-09-28 2010-02-23 Xilinx, Inc Flip-chip package having thermal expansion posts
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
SG136004A1 (en) * 2006-03-27 2007-10-29 Micron Techonology Inc Semiconductor constructions having interconnect structures, methods of forming interconnect structures, and methods of forming semiconductor constructions
US7473580B2 (en) * 2006-05-18 2009-01-06 International Business Machines Corporation Temporary chip attach using injection molded solder
US7638868B2 (en) * 2006-08-16 2009-12-29 Tessera, Inc. Microelectronic package
US7510401B2 (en) 2006-10-12 2009-03-31 Tessera, Inc. Microelectronic component with foam-metal posts
US7719121B2 (en) 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US7466154B2 (en) * 2006-10-18 2008-12-16 International Business Machines Corporation Conductive particle filled polymer electrical contact
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US8039960B2 (en) * 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
EP2206145A4 (en) 2007-09-28 2012-03-28 Tessera Inc FLIP-CHIP CONNECTION WITH DOUBLE POSTS
SG152101A1 (en) 2007-11-06 2009-05-29 Agency Science Tech & Res An interconnect structure and a method of fabricating the same
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US8697492B2 (en) * 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US9137903B2 (en) 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US10833033B2 (en) 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
US9105533B2 (en) * 2011-07-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure having a single side recess
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) * 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
TWI467718B (zh) * 2011-12-30 2015-01-01 Ind Tech Res Inst 凸塊結構以及電子封裝接點結構及其製造方法
US9159686B2 (en) 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
DE102012102021A1 (de) * 2012-03-09 2013-09-12 Epcos Ag Mikromechanisches Messelement und Verfahren zur Herstellung eines mikromechanischen Messelements
KR101932727B1 (ko) * 2012-05-07 2018-12-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 이의 제조 방법
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US20140035125A1 (en) * 2012-07-31 2014-02-06 Chipbond Technology Corporation Semiconductor manufacturing method, semiconductor structure and package structure thereof
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
EP2883245B1 (de) 2012-08-10 2020-09-30 SMARTRAC TECHNOLOGY GmbH Kontakthöckerverbindung sowie kontakthöcker und verfahren zur herstellung einer kontakthöckerverbindung
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9978667B2 (en) * 2013-08-07 2018-05-22 Texas Instruments Incorporated Semiconductor package with lead frame and recessed solder terminals
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9806045B2 (en) * 2013-08-29 2017-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9953198B2 (en) 2015-12-09 2018-04-24 Smartrac Technology Gmbh Systems and methods for a cloud connected transponder
US9692147B1 (en) * 2015-12-22 2017-06-27 Intel Corporation Small form factor sockets and connectors
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
DE102016121631A1 (de) * 2016-11-11 2018-05-17 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip, Anschlussträger für die Montage eines Halbleiterchips, Verfahren zur Herstellung eines optoelektronischen Bauteils und optoelektronisches Bauteil
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US20190355655A1 (en) * 2017-01-17 2019-11-21 Panasonic Intellectual Property Management Co, Ltd. Semiconductor-mounted product
US11676932B2 (en) * 2019-12-31 2023-06-13 Micron Technology, Inc. Semiconductor interconnect structures with narrowed portions, and associated systems and methods
JP2021125643A (ja) * 2020-02-07 2021-08-30 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3488840A (en) * 1963-12-27 1970-01-13 Ibm Method of connecting microminiaturized devices to circuit panels
US3470611A (en) * 1967-04-11 1969-10-07 Corning Glass Works Semiconductor device assembly method
US3921285A (en) * 1974-07-15 1975-11-25 Ibm Method for joining microminiature components to a carrying structure
JPS53106669U (ko) * 1977-01-31 1978-08-26
JPS56104445A (en) * 1980-01-25 1981-08-20 Hitachi Ltd Leadless semiconducdor device and junction structure for substrate
JPS58128749A (ja) * 1982-01-20 1983-08-01 ノ−ス・アメリカン・スペシヤリテイズ・コ−ポレイシヨン 電子的半組立部品用接続子
JPS6057957A (ja) * 1983-09-09 1985-04-03 Hitachi Micro Comput Eng Ltd 接続構造
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
JPS6151838A (ja) * 1984-08-22 1986-03-14 Hitachi Ltd 半導体装置
US4970570A (en) * 1986-10-28 1990-11-13 International Business Machines Corporation Use of tapered head pin design to improve the stress distribution in the braze joint
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US4845542A (en) * 1987-03-19 1989-07-04 Unisys Corporation Interconnect for layered integrated circuit assembly
FR2622741A1 (fr) * 1987-11-04 1989-05-05 Nec Corp Structure pour connexion de substrats a coefficients de dilatation thermique differents
JPH03268440A (ja) * 1990-03-19 1991-11-29 Hitachi Ltd 半導体チップの実装構造
JPH0732042B2 (ja) * 1990-10-11 1995-04-10 富士通株式会社 スルーホール接続形電子デバイスとその実装方法

Also Published As

Publication number Publication date
AU5771394A (en) 1994-09-15
CA2118649C (en) 2000-05-02
DE69428819D1 (de) 2001-12-06
CA2118649A1 (en) 1994-09-11
JP2716336B2 (ja) 1998-02-18
EP0615283A1 (en) 1994-09-14
AU675273B2 (en) 1997-01-30
KR0153212B1 (ko) 1998-12-01
JPH06268015A (ja) 1994-09-22
DE69428819T2 (de) 2002-06-20
US5640052A (en) 1997-06-17
EP0615283B1 (en) 2001-10-31

Similar Documents

Publication Publication Date Title
KR940022765A (ko) 반도체 장치의 상호 접속구조 및 상호접속 방법
US5968670A (en) Enhanced ceramic ball grid array using in-situ solder stretch with spring
KR100264638B1 (ko) 스트레스 경감을 위한 히트 싱크가 부착된 칼럼그리드 어레이
US6638638B2 (en) Hollow solder structure having improved reliability and method of manufacturing same
US5893725A (en) C4 substrate contact pad which has a layer of NI-B plating
US5463191A (en) Circuit board having an improved fine pitch ball grid array and method of assembly therefor
EP0624053B1 (en) Mounting device and method of connecting miniaturized electronic components by bump connections
US5337219A (en) Electronic package
US5964396A (en) Enhanced ceramic ball grid array using in-situ solder stretch with clip
US5975409A (en) Ceramic ball grid array using in-situ solder stretch
KR20040068169A (ko) 볼 그리드 배열 패케이지
JP6492768B2 (ja) 電子装置及びはんだ実装方法
JP2780631B2 (ja) 電子部品の接続構造およびその製造方法
US6600233B2 (en) Integrated circuit package with surface mounted pins on an organic substrate
US6133134A (en) Ball grid array integrated circuit package
JP3575324B2 (ja) 半導体装置、半導体装置の製造方法及び半導体装置の実装方法
JP2004079891A (ja) 配線基板、及び、配線基板の製造方法
JP3813767B2 (ja) 樹脂製配線基板及びその製造方法
JPH08236911A (ja) ボール状外部接続端子の構造
KR970018435A (ko) 반도체 패키지 실장방법
KR100499336B1 (ko) 플립칩 패키지소자와 제조방법
KR100233862B1 (ko) 반도체 패키지
JP2001189338A (ja) 半導体装置、半導体装置の製造方法及び試験方法
JPH05291432A (ja) 半導体パッケージ
JPH04268739A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee