KR930009114A - Mosfet 구조 및 그 제조방법 - Google Patents

Mosfet 구조 및 그 제조방법 Download PDF

Info

Publication number
KR930009114A
KR930009114A KR1019910017727A KR910017727A KR930009114A KR 930009114 A KR930009114 A KR 930009114A KR 1019910017727 A KR1019910017727 A KR 1019910017727A KR 910017727 A KR910017727 A KR 910017727A KR 930009114 A KR930009114 A KR 930009114A
Authority
KR
South Korea
Prior art keywords
polysilicon
oxide film
gate
undoped polysilicon
depositing
Prior art date
Application number
KR1019910017727A
Other languages
English (en)
Other versions
KR940010564B1 (ko
Inventor
장성진
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910017727A priority Critical patent/KR940010564B1/ko
Priority to DE4232820A priority patent/DE4232820B4/de
Priority to JP27163592A priority patent/JP3229665B2/ja
Priority to US07/959,882 priority patent/US5298443A/en
Publication of KR930009114A publication Critical patent/KR930009114A/ko
Application granted granted Critical
Publication of KR940010564B1 publication Critical patent/KR940010564B1/ko
Priority to US08/816,009 priority patent/US5834816A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

Abstract

내용 없음

Description

본 발명은 0.2급 MOSFET 제조방법 및 구조에 관한 것으로, 특히 일반적인 i라인 또는 g라인 포토 공정 사용에 적당하도록 한 사이드 월 소스/드레인과 자기 정렬 게이트 형성 및 콘택 공정을 포함하느 MOSFET 제조방법 및 구조에 관한 것이다. 이를 위하여 본 발명에서는, MOSFET 제조방법에 있어서, 실리콘 기판상에 LOCOS 공정으로 활성영역을 정의한 다음, 패드 산화막, 언드포된(Undoped)폴리 실리콘 또는 폴리사이드, CVD 산화막을 순서대로 데포지션하고 마스크를 사용하여 MOSFET가 형성될 부분을 정의한 단계(a)와, RIE(Reactive Ion Etching)를 이용하여 상기 CVD 산화막, 언도프된 폴리실리콘 또는 폴리사이드, 패드 산화막을 에치하고 채널이온주입을 실시하는 단계(b)와, 언도프된 폴리실리콘으 데포지션하는 단계(c)와, RIE하여 상기 언도프드 폴리실리콘 사이드 월을 형성하는 단계(d)와, 실리콘 에치 데미지(damage) 제거를 위해 아닐링(annealing)을 하고, 이때 자라난 산화막을 제거하며, 게이트 산화를 수행하고 게이트 폴리실리콘을 데포지션하는 단계(e)와, 콘 사이드 월을 평평하게 하며, 소스/드레인 이온 주입을 실시하여 소스/드레인 이온 주입을 실시하여 소스/드레인 영역을 형성하는 단계(g)와, 절연물로 사용되는 산화막을 데포지션한 다음 콘택을 형성하고 메탈을 데포지션하는 단계(h)를 구비하는 것을 특징으로 하는 MOSFET 제조방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 MOSFET 제조 공정도.

Claims (3)

  1. MOSFET 제조방법에 있어서, 실리콘 기판상에 LOCOS 공정으로 활성영역을 정의한 다음, 패드 산화막, 언드프드(Undoped)폴리 실리콘 또는 폴리사이드, CVD 산화막을 순서대로 데포지션하고 마스크를 사용하여 MOSFET가 형성될 부분을 정의한 단계(a)와, RIE(Reactive Ion Etching)를 이용하여 상기 CVD 산화막, 언도프드 폴리실리콘 또는 폴리사이드, 패드 산화막을 에치하고 채널이온주입을 실시하는 단계(b)와, 언도프드 폴리실리콘을 데포지션하는 단계(c)와, RIE하여 상기 언도프드 폴리실리콘 사이드 월을 형성하는 단계(d)와, 실리콘 에치 데미지(damage) 제거를 위해 아닐링(annealing)을 하고, 이때 자라난 산화막을 제거하며, 게이트 산화를 수행하고 게이트 폴리실리콘을 데포지션하는 단계(e)와, RIE하여 게이트 폴리 실리콘을 일부 남기고 게이트 폴리실리콘 절연을 위한 산화막을 데포지션하는 단계(f)와, 상기 절연용 산화막을 RIE하고 다시 폴리실리콘을 RIE하여 언도프드 폴리시릴콘 콘 사이드 월을 평평하게 하며, 소스/드레인 이온 주입을 실시하여 소스/드레인 이온 주입을 실시하여 소스/드레인 영역을 형성하는 단계(g)와, 절연물로 사용되는 산화막을 데포지션한 다음 콘택을 형성하고 메탈을 데포지션하는 단계(h)를 구비하는 것을 특징으로 하는 MOSFET 제조방법.
  2. 제1항에 있어서, 단계(g)에서, 산화막과 언도프드 폴리 실리콘 사이드 월의 에티 비율은 1 : 1로 하는 것을 특징으로 하는 MOSFET 제조방법.
  3. MOSFET 구조에 있어서, 게이트 산화막 상의 게이트 폴리 실리콘 위에는 게이트 폴리 실리콘과 같은 폭으로 절연용 산화막이 놓이고, 상기 게이트 폴리 실리콘 및 절연용 산화막 좌우에는 각각 산화막, 언도프드(Undoped) 폴리실리콘, 패드 산화막과 언도프드 폴리실리콘 또는 폴리사이드 그리고 CVD 산화막의 적층 구조가 차례로 배치되며, 상기 게이트 폴리 실리콘 좌우의 산화막 및 언도프드 폴리 실리콘 하부에는 소스/드레인 영역이 형성되며, 상기 적층 구조의 하부에는 필드 산화막이, 상부에는 메탈이 형성되는 것을 특징으로 하는 MOSFET 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910017727A 1991-10-10 1991-10-10 전계효과 트랜지스터 및 그 제조방법 KR940010564B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019910017727A KR940010564B1 (ko) 1991-10-10 1991-10-10 전계효과 트랜지스터 및 그 제조방법
DE4232820A DE4232820B4 (de) 1991-10-10 1992-09-30 Verfahren zur Herstellung eines MOSFET
JP27163592A JP3229665B2 (ja) 1991-10-10 1992-10-09 Ｍｏｓｆｅｔの製造方法
US07/959,882 US5298443A (en) 1991-10-10 1992-10-13 Process for forming a MOSFET
US08/816,009 US5834816A (en) 1991-10-10 1997-03-10 MOSFET having tapered gate electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910017727A KR940010564B1 (ko) 1991-10-10 1991-10-10 전계효과 트랜지스터 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR930009114A true KR930009114A (ko) 1993-05-22
KR940010564B1 KR940010564B1 (ko) 1994-10-24

Family

ID=19320989

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910017727A KR940010564B1 (ko) 1991-10-10 1991-10-10 전계효과 트랜지스터 및 그 제조방법

Country Status (4)

Country Link
US (2) US5298443A (ko)
JP (1) JP3229665B2 (ko)
KR (1) KR940010564B1 (ko)
DE (1) DE4232820B4 (ko)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376578A (en) * 1993-12-17 1994-12-27 International Business Machines Corporation Method of fabricating a semiconductor device with raised diffusions and isolation
KR100255512B1 (ko) * 1996-06-29 2000-05-01 김영환 플래쉬 메모리 소자 제조방법
EP0908934B1 (en) * 1997-10-07 2008-12-31 Texas Instruments Incorporated Method of manufacturing a gate electrode
US6140677A (en) * 1998-06-26 2000-10-31 Advanced Micro Devices, Inc. Semiconductor topography for a high speed MOSFET having an ultra narrow gate
US5998847A (en) * 1998-08-11 1999-12-07 International Business Machines Corporation Low voltage active body semiconductor device
US6018179A (en) * 1998-11-05 2000-01-25 Advanced Micro Devices Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties
SE9901092L (sv) 1999-03-25 2000-09-26 Valmet Karlstad Ab Upphängningsanordning för en vals
JP2000332242A (ja) * 1999-05-21 2000-11-30 Mitsubishi Electric Corp 半導体装置及びその製造方法
TW490713B (en) * 1999-07-22 2002-06-11 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
JP2002170941A (ja) * 2000-12-01 2002-06-14 Nec Corp 半導体装置及びその製造方法
JP2002373909A (ja) * 2001-06-15 2002-12-26 Mitsubishi Electric Corp 半導体回路装置及びその製造方法
US6784491B2 (en) * 2002-09-27 2004-08-31 Intel Corporation MOS devices with reduced fringing capacitance
US7208361B2 (en) * 2004-03-24 2007-04-24 Intel Corporation Replacement gate process for making a semiconductor device that includes a metal gate electrode
JP2009302317A (ja) * 2008-06-13 2009-12-24 Renesas Technology Corp 半導体装置およびその製造方法
US8076735B2 (en) * 2009-10-02 2011-12-13 United Microelectronics Corp. Semiconductor device with trench of various widths
US9018024B2 (en) * 2009-10-22 2015-04-28 International Business Machines Corporation Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness
US8110483B2 (en) 2009-10-22 2012-02-07 International Business Machines Corporation Forming an extremely thin semiconductor-on-insulator (ETSOI) layer
US8124427B2 (en) 2009-10-22 2012-02-28 International Business Machines Corporation Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness
KR102167625B1 (ko) * 2013-10-24 2020-10-19 삼성전자주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
US4442591A (en) * 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
JPS6235570A (ja) * 1985-08-08 1987-02-16 Fujitsu Ltd 半導体装置の製造方法
JPS62147777A (ja) * 1985-12-20 1987-07-01 Mitsubishi Electric Corp Ｍｏｓ形電界効果トランジスタの製造方法
JPS62235783A (ja) * 1986-04-07 1987-10-15 Matsushita Electronics Corp 電界効果トランジスタの製造方法
US4939154A (en) * 1987-03-25 1990-07-03 Seiko Instruments Inc. Method of fabricating an insulated gate semiconductor device having a self-aligned gate
US5175118A (en) * 1988-09-20 1992-12-29 Mitsubishi Denki Kabushiki Kaisha Multiple layer electrode structure for semiconductor device and method of manufacturing thereof
JPH0728040B2 (ja) * 1988-09-20 1995-03-29 三菱電機株式会社 半導体装置およびその製造方法
US5141891A (en) * 1988-11-09 1992-08-25 Mitsubishi Denki Kabushiki Kaisha MIS-type semiconductor device of LDD structure and manufacturing method thereof
KR920003461A (ko) * 1990-07-30 1992-02-29 김광호 접촉영역 형성방법 및 그를 이용한 반도체장치의 제조방법
US5196357A (en) * 1991-11-18 1993-03-23 Vlsi Technology, Inc. Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor

Also Published As

Publication number Publication date
JP3229665B2 (ja) 2001-11-19
US5834816A (en) 1998-11-10
DE4232820A1 (de) 1993-04-22
DE4232820B4 (de) 2005-11-17
KR940010564B1 (ko) 1994-10-24
US5298443A (en) 1994-03-29
JPH05206451A (ja) 1993-08-13

Similar Documents

Publication Publication Date Title
KR930009114A (ko) Mosfet 구조 및 그 제조방법
KR100639971B1 (ko) 리세스된 소스/드레인 구조를 갖는 초박막의 에스오아이모스 트랜지스터 및 그 제조방법
US20020009859A1 (en) Method for making SOI MOSFET
US5527725A (en) Method for fabricating a metal oxide semiconductor field effect transistor
JPS63257231A (ja) 半導体装置の製造方法
JPH07302804A (ja) 半導体素子のチャネル領域製造方法
KR0170515B1 (ko) Gold구조를 갖는 반도체장치 및 그의 제조방법
JPH06349856A (ja) 薄膜トランジスタ及びその製造方法
JPH02260564A (ja) 半導体装置及びその製造方法
KR0151066B1 (ko) 게이트 전극으로 티타늄 질화막을 사용하는 반도체 장치의 제조방법
KR0135041B1 (ko) Soi mosfet 제조방법
KR960002083B1 (ko) 모스 페트 제조 방법
JPH098308A (ja) 半導体素子のトランジスター及びその製造方法
KR20000012100A (ko) 반도체 장치 및 그 제조 방법
KR930009479B1 (ko) 절연게이트형 전계효과 트랜지스터 제조방법
JPH05190854A (ja) 半導体装置の製造方法
KR0147255B1 (ko) Mosfet의 제조방법
KR930001893B1 (ko) 씨모스 트랜지스터 제조방법
KR920005373A (ko) 수직모스 트랜지스터 제조방법
JPH03215945A (ja) Ｌｄｄ構造ｍｏｓｆｅｔの製造方法
JPH07106556A (ja) 半導体装置の製造方法
KR920007181A (ko) 앤-모스 ldd트랜지스터의 제조방법
KR960005998A (ko) 반도체 소자 및 그 제조방법
JPS61166154A (ja) Ｍｉｓ型半導体装置の製造方法
JPH02295131A (ja) Ｍｏｓトランジスタの製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090922

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee