KR870008381A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR870008381A
KR870008381A KR870000661A KR870000661A KR870008381A KR 870008381 A KR870008381 A KR 870008381A KR 870000661 A KR870000661 A KR 870000661A KR 870000661 A KR870000661 A KR 870000661A KR 870008381 A KR870008381 A KR 870008381A
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KR
South Korea
Prior art keywords
semiconductor
ferret
semiconductor device
recess
metal layer
Prior art date
Application number
KR870000661A
Other languages
English (en)
Inventor
히로시 야마모도
Original Assignee
나가이 아쯔시
히다찌마구세루 가부시기 가이샤
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Application filed by 나가이 아쯔시, 히다찌마구세루 가부시기 가이샤 filed Critical 나가이 아쯔시
Publication of KR870008381A publication Critical patent/KR870008381A/ko

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 관한 반도체 장치의 중요부의 단면도.
제 2 도는 웨이퍼의 뒷면에 형성되는 금속층이 상태를 도시한 반도체의 확대 단면도.
제 3 도는 확산의 초기 단계를 도시한 반도체의 확대 단면도.

Claims (10)

  1. 소정의 위치에 반도체 페렛을 내장 가능한 오목함부가 마련된 플라스틱 재료로 되는 배선기관의 해당 오목함부내에 반도체 소자가 형성되어 있지 않은 면에 금속층이 형성된 반도체 페렛을 설치하고, 그 반도체페렛을 설치한 상기 오목함부내를 고분자 재료로 봉지한 것을 특징으로 하는 반도체 장치.
  2. 적어도 페렛과 금속층과의 계면에 있어서, 페렛을 형성하는 원소와 금속층을 형성하는 금속 원소와의 합금층이 형성되어 있는 반도체 페렛을 사용한 것을 특징으로 하는 특허 청구의 범위 제 1 항 기재의 반도체장치.
  3. 금, 은, 니켈, 알미늄, 크롬, 몰리브텐에서 선택된 적어도 1종류의 금속을 사용하여 금속층이 형성된 반도체 페렛을 사용한 것을 특징으로 하는 특허청구의 범위 제 1 항과 제 2 항 기재의 반도체장치.
  4. 금속층의 두께가 20㎛이하로 형성된 반도체 페렛을 사용한 것을 특징으로 하는 특허청구의 범위 제 1 항 내지 제 3 항 기재의 반도체 장치.
  5. 반도체 소자가 형성되어 있지 않은 면을 연마한 박형 페렛에 있어서, 그 연마면이 경면(鏡面)이 완성되지 않은 반도체 페렛을 사용한 것을 특징으로 하는 특허청구의 범위 제 1 항 내지 제 4 항 기재의 반도체장치.
  6. 배선 기판이 폴리이미드 수지로 형성되어 있는 것을 특징으로 하는 특허 청구의 범위 제 1 항 기재의 반도체장치.
  7. 반도체 페렛의 두께가 0.4mm이하인 것을 특징으로 하는 특허청구의 범위 제 1 항 내지 제 5 항 기재의 반도체장치.
  8. 반도체 페렛과 배선기판을 와이어 본딩으로 접속한 것을 특징으로 하는 특허청구의 범위 제 1 항 기재의 반도체 장치.
  9. 반도체 페렛을 배선 기판의 오목함부내에 에폭시 수지로 봉지한 것을 특징으로 하는 특허청구의 범위 제 1 항 기재의 반도체 장치.
  10. 반도체 페렛을 배선 기판의 오목함부내에 아크릴 수지로 봉지한 것을 특징으로 하는 특허청구의 범위 제 1 항 기재의 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR870000661A 1986-02-06 1987-01-28 반도체 장치 KR870008381A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61022960A JP2502511B2 (ja) 1986-02-06 1986-02-06 半導体装置の製造方法
JP22960 1986-02-06

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KR870008381A true KR870008381A (ko) 1987-09-26

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DE (1) DE3788362T2 (ko)

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DE3788362D1 (de) 1994-01-20
JPS62183151A (ja) 1987-08-11
JP2502511B2 (ja) 1996-05-29
DE3788362T2 (de) 1994-03-24
EP0231937B1 (en) 1993-12-08
EP0231937A3 (en) 1989-03-22
EP0231937A2 (en) 1987-08-12
US4961105A (en) 1990-10-02

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