KR870007515A - 반도체 기억회로 - Google Patents

반도체 기억회로

Info

Publication number
KR870007515A
KR870007515A KR1019860006842A KR860006842A KR870007515A KR 870007515 A KR870007515 A KR 870007515A KR 1019860006842 A KR1019860006842 A KR 1019860006842A KR 860006842 A KR860006842 A KR 860006842A KR 870007515 A KR870007515 A KR 870007515A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
memory circuit
circuit
semiconductor
memory
Prior art date
Application number
KR1019860006842A
Other languages
English (en)
Other versions
KR900002665B1 (ko
Inventor
요이찌 도비다
Original Assignee
미쓰비시전기 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰비시전기 주식회사 filed Critical 미쓰비시전기 주식회사
Publication of KR870007515A publication Critical patent/KR870007515A/ko
Application granted granted Critical
Publication of KR900002665B1 publication Critical patent/KR900002665B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
KR1019860006842A 1986-01-21 1986-08-19 반도체 기억회로 KR900002665B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61-12319 1986-01-21
JP61012319A JPS62170094A (ja) 1986-01-21 1986-01-21 半導体記憶回路

Publications (2)

Publication Number Publication Date
KR870007515A true KR870007515A (ko) 1987-08-19
KR900002665B1 KR900002665B1 (ko) 1990-04-21

Family

ID=11801989

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860006842A KR900002665B1 (ko) 1986-01-21 1986-08-19 반도체 기억회로

Country Status (4)

Country Link
US (2) US4860259A (ko)
JP (1) JPS62170094A (ko)
KR (1) KR900002665B1 (ko)
DE (1) DE3639169A1 (ko)

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US5245577A (en) * 1990-11-06 1993-09-14 Micron Technology, Inc. Integrated circuit two-cycle test mode activation circuit
US5974570A (en) * 1990-12-01 1999-10-26 Hitachi, Ltd. Method for managing data processing system and high-reliability memory
JP2863012B2 (ja) * 1990-12-18 1999-03-03 三菱電機株式会社 半導体記憶装置
US5231605A (en) * 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
KR930009490B1 (ko) * 1991-07-15 1993-10-04 금성일렉트론 주식회사 순간 테스트 모드 지정회로
US5850509A (en) * 1991-11-13 1998-12-15 Intel Corporation Circuitry for propagating test mode signals associated with a memory array
US5285419A (en) * 1991-12-17 1994-02-08 Sgs-Thomson Microelectronics, Inc. Read/write memory with improved test mode data compare
JP2856598B2 (ja) * 1992-06-04 1999-02-10 三菱電機株式会社 ダイナミックランダムアクセスメモリ装置
JP3007475B2 (ja) * 1992-06-05 2000-02-07 三菱電機株式会社 メモリ装置
KR960005387Y1 (ko) * 1992-09-24 1996-06-28 문정환 반도체 메모리의 번 인 테스트(Burn-In Test) 장치
US6105152A (en) 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
US5864565A (en) * 1993-06-15 1999-01-26 Micron Technology, Inc. Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
US5383157A (en) * 1993-08-06 1995-01-17 Cypress Semiconductor Corporation Parallel TESTMODE
ATE173111T1 (de) * 1994-04-29 1998-11-15 Texas Instruments Inc Verfahren und vorrichtung zur prüfung eines speichers mit einer parallelen block-schreib- operation
DE4422173C2 (de) * 1994-06-28 2000-02-03 Mannesmann Vdo Ag Schaltungsanordnung zur Umschaltung eines sich in einem Steuersystem befindenden Mikroprozessors in einen Boots-Trap-Modus, insbesondere für ein Kraftfahrzeug
US5982188A (en) * 1994-07-29 1999-11-09 Stmicroelectronics, Inc. Test mode control circuit of an integrated circuit device
US5533194A (en) * 1994-12-28 1996-07-02 International Business Machines Corporation Hardware-assisted high speed memory test apparatus and method
US5619460A (en) * 1995-06-07 1997-04-08 International Business Machines Corporation Method of testing a random access memory
US5615164A (en) * 1995-06-07 1997-03-25 International Business Machines Corporation Latched row decoder for a random access memory
US5675540A (en) * 1996-01-22 1997-10-07 Micron Quantum Devices, Inc. Non-volatile memory system having internal data verification test mode
US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
US5848017A (en) 1997-09-30 1998-12-08 Micron Technology, Inc. Method and apparatus for stress testing a semiconductor memory
KR100267781B1 (ko) * 1998-03-04 2000-10-16 김영환 테스트 모드를 셋업하기 위한 반도체 소자
JP2001202797A (ja) * 2000-01-20 2001-07-27 Mitsubishi Electric Corp 半導体記憶装置および半導体テスト方法
DE10064478B4 (de) 2000-12-22 2005-02-24 Atmel Germany Gmbh Verfahren zur Prüfung einer integrierten Schaltung und Schaltungsanordnung
US6515904B2 (en) 2001-03-21 2003-02-04 Matrix Semiconductor, Inc. Method and system for increasing programming bandwidth in a non-volatile memory device
US6574145B2 (en) 2001-03-21 2003-06-03 Matrix Semiconductor, Inc. Memory device and method for sensing while programming a non-volatile memory cell
DE10219782C1 (de) * 2002-05-03 2003-11-13 Infineon Technologies Ag Verfahren und Hilfseinrichtung zum Testen einer RAM-Speicherschaltung
DE10344879B4 (de) * 2003-09-26 2005-11-24 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Funktionstest des integrierten Speichers
US7888962B1 (en) 2004-07-07 2011-02-15 Cypress Semiconductor Corporation Impedance matching circuit
US7675790B1 (en) * 2005-09-30 2010-03-09 Integrated Device Technology, Inc. Over driving pin function selection method and circuit
US8036846B1 (en) 2005-10-20 2011-10-11 Cypress Semiconductor Corporation Variable impedance sense architecture and method
KR20160116913A (ko) * 2015-03-31 2016-10-10 에스케이하이닉스 주식회사 상태 페일 신호를 출력하는 반도체 메모리 장치 및 그것의 동작 방법

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JPS59107493A (ja) * 1982-12-09 1984-06-21 Ricoh Co Ltd テスト回路付きｅｐｒｏｍメモリ装置
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ATE53261T1 (de) * 1985-03-26 1990-06-15 Siemens Ag Verfahren zum betreiben eines halbleiterspeichers mit integrierter paralleltestmoeglichkeit und auswerteschaltung zur durchfuehrung des verfahrens.
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Also Published As

Publication number Publication date
DE3639169A1 (de) 1987-07-23
KR900002665B1 (ko) 1990-04-21
US4860259A (en) 1989-08-22
DE3639169C2 (ko) 1989-06-22
JPS62170094A (ja) 1987-07-27
USRE34718E (en) 1994-09-06

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A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
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Year of fee payment: 17

EXPY Expiration of term