KR890004320A - 지연 회로를 갖는 반도체 메모리 회로 - Google Patents
지연 회로를 갖는 반도체 메모리 회로Info
- Publication number
- KR890004320A KR890004320A KR1019880009947A KR880009947A KR890004320A KR 890004320 A KR890004320 A KR 890004320A KR 1019880009947 A KR1019880009947 A KR 1019880009947A KR 880009947 A KR880009947 A KR 880009947A KR 890004320 A KR890004320 A KR 890004320A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- semiconductor memory
- delay
- delay circuit
- memory circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP197894 | 1987-08-07 | ||
JP62197894A JP2590122B2 (ja) | 1987-08-07 | 1987-08-07 | 半導体メモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890004320A true KR890004320A (ko) | 1989-04-21 |
KR920001324B1 KR920001324B1 (ko) | 1992-02-10 |
Family
ID=16382059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880009947A KR920001324B1 (ko) | 1987-08-07 | 1988-08-04 | 지연 회로를 갖는 반도체 메모리 회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4866675A (ko) |
EP (1) | EP0302795B1 (ko) |
JP (1) | JP2590122B2 (ko) |
KR (1) | KR920001324B1 (ko) |
DE (1) | DE3885532T2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100421341B1 (ko) * | 2002-02-09 | 2004-03-06 | 주식회사 연우이앤티 | 전자식 교환기의 국선 정합장치 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5014242A (en) * | 1987-12-10 | 1991-05-07 | Hitachi, Ltd. | Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit |
US5031150A (en) * | 1988-08-26 | 1991-07-09 | Kabushiki Kaisha Toshiba | Control circuit for a semiconductor memory device and semiconductor memory system |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
JP2977296B2 (ja) * | 1991-02-19 | 1999-11-15 | 沖電気工業株式会社 | 半導体メモリ装置 |
US5303191A (en) * | 1992-01-23 | 1994-04-12 | Motorola, Inc. | Memory with compensation for voltage, temperature, and processing variations |
JP2716912B2 (ja) * | 1992-07-23 | 1998-02-18 | 株式会社東芝 | 半導体記憶装置 |
US5574866A (en) * | 1993-04-05 | 1996-11-12 | Zenith Data Systems Corporation | Method and apparatus for providing a data write signal with a programmable duration |
US5424985A (en) * | 1993-06-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Compensating delay element for clock generation in a memory device |
JPH07141250A (ja) * | 1993-09-20 | 1995-06-02 | Fujitsu Ltd | メモリ制御装置 |
US5406518A (en) * | 1994-02-08 | 1995-04-11 | Industrial Technology Research Institute | Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration |
JP3394111B2 (ja) * | 1995-05-25 | 2003-04-07 | 株式会社 沖マイクロデザイン | 半導体記憶装置のデータ入力回路 |
US6470405B2 (en) | 1995-10-19 | 2002-10-22 | Rambus Inc. | Protocol for communication with dynamic memory |
US6810449B1 (en) | 1995-10-19 | 2004-10-26 | Rambus, Inc. | Protocol for communication with dynamic memory |
US6035369A (en) | 1995-10-19 | 2000-03-07 | Rambus Inc. | Method and apparatus for providing a memory with write enable information |
US6088774A (en) | 1996-09-20 | 2000-07-11 | Advanced Memory International, Inc. | Read/write timing for maximum utilization of bidirectional read/write bus |
US5964884A (en) * | 1996-09-30 | 1999-10-12 | Advanced Micro Devices, Inc. | Self-timed pulse control circuit |
US6266379B1 (en) | 1997-06-20 | 2001-07-24 | Massachusetts Institute Of Technology | Digital transmitter with equalization |
US6401167B1 (en) | 1997-10-10 | 2002-06-04 | Rambus Incorporated | High performance cost optimized memory |
AU9604698A (en) | 1997-10-10 | 1999-05-03 | Rambus Incorporated | Method and apparatus for two step memory write operations |
JP4190662B2 (ja) * | 1999-06-18 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置及びタイミング制御回路 |
US8391039B2 (en) | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US7301831B2 (en) | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
KR100795007B1 (ko) * | 2006-06-27 | 2008-01-16 | 주식회사 하이닉스반도체 | 동기회로의 지연 장치 및 그 제어방법 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5587384A (en) * | 1978-12-22 | 1980-07-02 | Hitachi Ltd | Semiconductor memory circuit |
JPS5634186A (en) * | 1979-08-29 | 1981-04-06 | Hitachi Ltd | Bipolar memory circuit |
DE2952056C2 (de) * | 1979-12-22 | 1981-11-26 | Hewlett-Packard GmbH, 7030 Böblingen | Schreib- und Leseschaltung für einen Speicher mit wahlfreiem Zugriff |
US4425633A (en) * | 1980-10-06 | 1984-01-10 | Mostek Corporation | Variable delay circuit for emulating word line delay |
JPS58203694A (ja) * | 1982-05-21 | 1983-11-28 | Nec Corp | メモリ回路 |
JPS58220291A (ja) * | 1982-06-15 | 1983-12-21 | Nec Corp | 信号伝般時間制御回路 |
US4740923A (en) * | 1985-11-19 | 1988-04-26 | Hitachi, Ltd | Memory circuit and method of controlling the same |
-
1987
- 1987-08-07 JP JP62197894A patent/JP2590122B2/ja not_active Expired - Fee Related
-
1988
- 1988-08-03 EP EP88402034A patent/EP0302795B1/en not_active Expired - Lifetime
- 1988-08-03 DE DE88402034T patent/DE3885532T2/de not_active Expired - Fee Related
- 1988-08-04 KR KR1019880009947A patent/KR920001324B1/ko not_active IP Right Cessation
- 1988-08-05 US US07/228,463 patent/US4866675A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100421341B1 (ko) * | 2002-02-09 | 2004-03-06 | 주식회사 연우이앤티 | 전자식 교환기의 국선 정합장치 |
Also Published As
Publication number | Publication date |
---|---|
US4866675A (en) | 1989-09-12 |
DE3885532D1 (de) | 1993-12-16 |
EP0302795A2 (en) | 1989-02-08 |
DE3885532T2 (de) | 1994-03-31 |
EP0302795A3 (en) | 1991-03-06 |
JP2590122B2 (ja) | 1997-03-12 |
EP0302795B1 (en) | 1993-11-10 |
KR920001324B1 (ko) | 1992-02-10 |
JPS6442096A (en) | 1989-02-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20040120 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |