KR20110121671A - 마스터 디바이스를 포함하는 적층형 반도체 디바이스 - Google Patents

마스터 디바이스를 포함하는 적층형 반도체 디바이스 Download PDF

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KR20110121671A
KR20110121671A KR1020117009171A KR20117009171A KR20110121671A KR 20110121671 A KR20110121671 A KR 20110121671A KR 1020117009171 A KR1020117009171 A KR 1020117009171A KR 20117009171 A KR20117009171 A KR 20117009171A KR 20110121671 A KR20110121671 A KR 20110121671A
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South Korea
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chip
nonvolatile memory
region
memory chip
additional
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Korean (ko)
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진기 김
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모사이드 테크놀로지스 인코퍼레이티드
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732Location after the connecting process
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    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
KR1020117009171A 2009-02-24 2010-02-12 마스터 디바이스를 포함하는 적층형 반도체 디바이스 Ceased KR20110121671A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15491009P 2009-02-24 2009-02-24
US61/154,910 2009-02-24
US12/429,310 2009-04-24
US12/429,310 US7894230B2 (en) 2009-02-24 2009-04-24 Stacked semiconductor devices including a master device

Publications (1)

Publication Number Publication Date
KR20110121671A true KR20110121671A (ko) 2011-11-08

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Application Number Title Priority Date Filing Date
KR1020117009171A Ceased KR20110121671A (ko) 2009-02-24 2010-02-12 마스터 디바이스를 포함하는 적층형 반도체 디바이스

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US (4) US7894230B2 (enExample)
EP (1) EP2401745A1 (enExample)
JP (2) JP2012518859A (enExample)
KR (1) KR20110121671A (enExample)
CN (2) CN104332179A (enExample)
DE (1) DE112010000880T5 (enExample)
TW (1) TW201101464A (enExample)
WO (1) WO2010096901A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150087343A (ko) * 2012-11-19 2015-07-29 실리콘 스토리지 테크놀로지 인크 3차원 플래시 메모리 시스템
KR20190084854A (ko) * 2018-01-09 2019-07-17 윈본드 일렉트로닉스 코포레이션 반도체 기억장치

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007002324A2 (en) * 2005-06-24 2007-01-04 Metaram, Inc. An integrated memory core and memory interface circuit
US9251899B2 (en) * 2008-02-12 2016-02-02 Virident Systems, Inc. Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers
WO2010047140A1 (ja) * 2008-10-20 2010-04-29 国立大学法人東京大学 集積回路装置
US7894230B2 (en) * 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device
US20100332177A1 (en) * 2009-06-30 2010-12-30 National Tsing Hua University Test access control apparatus and method thereof
KR20110052133A (ko) * 2009-11-12 2011-05-18 주식회사 하이닉스반도체 반도체 장치
US8159075B2 (en) * 2009-12-18 2012-04-17 United Microelectronics Corp. Semiconductor chip stack and manufacturing method thereof
KR101046273B1 (ko) * 2010-01-29 2011-07-04 주식회사 하이닉스반도체 반도체 장치
US20110272788A1 (en) * 2010-05-10 2011-11-10 International Business Machines Corporation Computer system wafer integrating different dies in stacked master-slave structures
KR101085724B1 (ko) * 2010-05-10 2011-11-21 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 동작 방법
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8625352B2 (en) * 2010-11-23 2014-01-07 Mosaid Technologies Incorporated Method and apparatus for sharing internal power supplies in integrated circuit devices
KR101854251B1 (ko) 2010-11-30 2018-05-03 삼성전자주식회사 멀티 채널 반도체 메모리 장치 및 그를 구비하는 반도체 장치
JP2012146377A (ja) * 2011-01-14 2012-08-02 Elpida Memory Inc 半導体装置
JP5647026B2 (ja) * 2011-02-02 2014-12-24 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体装置及びその製造方法
US9432298B1 (en) 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
KR20120122549A (ko) 2011-04-29 2012-11-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 리페어 방법
US10141314B2 (en) * 2011-05-04 2018-11-27 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
DE112011106009T5 (de) * 2011-12-23 2014-12-18 Intel Corp. Getrennte Mikrokanal-Spannungsdomänen in Stapelspeicherarchitektur
US10355001B2 (en) 2012-02-15 2019-07-16 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
KR101805343B1 (ko) 2012-03-20 2017-12-05 인텔 코포레이션 동작 제어를 위한 장치 명령에 응답하는 메모리 장치
KR20140008766A (ko) * 2012-07-11 2014-01-22 에스케이하이닉스 주식회사 반도체메모리장치
US9391453B2 (en) * 2013-06-26 2016-07-12 Intel Corporation Power management in multi-die assemblies
US20150019802A1 (en) * 2013-07-11 2015-01-15 Qualcomm Incorporated Monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning
US9047953B2 (en) * 2013-08-22 2015-06-02 Macronix International Co., Ltd. Memory device structure with page buffers in a page-buffer level separate from the array level
KR20150056309A (ko) * 2013-11-15 2015-05-26 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
US20150155039A1 (en) * 2013-12-02 2015-06-04 Silicon Storage Technology, Inc. Three-Dimensional Flash NOR Memory System With Configurable Pins
US9281302B2 (en) 2014-02-20 2016-03-08 International Business Machines Corporation Implementing inverted master-slave 3D semiconductor stack
KR102229942B1 (ko) 2014-07-09 2021-03-22 삼성전자주식회사 멀티 다이들을 갖는 멀티 채널 반도체 장치의 동작 방법 및 그에 따른 반도체 장치
KR102179297B1 (ko) 2014-07-09 2020-11-18 삼성전자주식회사 모노 패키지 내에서 인터커넥션을 가지는 반도체 장치 및 그에 따른 제조 방법
US9711224B2 (en) 2015-03-13 2017-07-18 Micron Technology, Inc. Devices including memory arrays, row decoder circuitries and column decoder circuitries
JP2016168780A (ja) * 2015-03-13 2016-09-23 富士フイルム株式会社 液体供給装置及び画像形成装置
KR102449571B1 (ko) 2015-08-07 2022-10-04 삼성전자주식회사 반도체 장치
US10020252B2 (en) * 2016-11-04 2018-07-10 Micron Technology, Inc. Wiring with external terminal
US10141932B1 (en) 2017-08-04 2018-11-27 Micron Technology, Inc. Wiring with external terminal
US10304497B2 (en) 2017-08-17 2019-05-28 Micron Technology, Inc. Power supply wiring in a semiconductor memory device
JP6444475B1 (ja) 2017-11-28 2018-12-26 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
JP6395919B1 (ja) 2017-12-13 2018-09-26 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
JP6482690B1 (ja) 2018-01-11 2019-03-13 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
KR102532205B1 (ko) 2018-07-09 2023-05-12 삼성전자 주식회사 반도체 칩 및 그 반도체 칩을 포함한 반도체 패키지
US10860918B2 (en) * 2018-08-21 2020-12-08 Silicon Storage Technology, Inc. Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components
KR102670866B1 (ko) * 2018-11-28 2024-05-30 삼성전자주식회사 복수의 메모리 플레인들을 포함하는 비휘발성 메모리 장치 및 이를 포함하는 메모리 시스템
US11657858B2 (en) 2018-11-28 2023-05-23 Samsung Electronics Co., Ltd. Nonvolatile memory devices including memory planes and memory systems including the same
US10777232B2 (en) * 2019-02-04 2020-09-15 Micron Technology, Inc. High bandwidth memory having plural channels
CN113051199A (zh) 2019-12-26 2021-06-29 阿里巴巴集团控股有限公司 数据传输方法及装置
TWI735391B (zh) * 2020-09-30 2021-08-01 創意電子股份有限公司 具有通信介面的半導體器件及半導體器件的介面管理方法
TWI744113B (zh) * 2020-09-30 2021-10-21 創意電子股份有限公司 用於三維半導體器件的介面器件及介面方法
CN119698936A (zh) * 2023-07-25 2025-03-25 长江存储科技有限责任公司 芯片封装结构及其制备方法、存储系统、电子设备

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399898A (en) 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JPH0812754B2 (ja) * 1990-08-20 1996-02-07 富士通株式会社 昇圧回路
JPH04107617A (ja) * 1990-08-28 1992-04-09 Seiko Epson Corp 半導体装置
JPH05275657A (ja) * 1992-03-26 1993-10-22 Toshiba Corp 半導体記憶装置
JP2605968B2 (ja) * 1993-04-06 1997-04-30 日本電気株式会社 半導体集積回路およびその形成方法
US5579207A (en) 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking
JP3517489B2 (ja) * 1995-09-04 2004-04-12 株式会社日立製作所 不揮発性半導体記憶装置
US5818107A (en) 1997-01-17 1998-10-06 International Business Machines Corporation Chip stacking by edge metallization
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
JP3557114B2 (ja) * 1998-12-22 2004-08-25 株式会社東芝 半導体記憶装置
JP3662461B2 (ja) 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
US6376904B1 (en) 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
TW521858U (en) 2000-04-28 2003-02-21 Agc Technology Inc Integrated circuit apparatus with expandable memory
US6404043B1 (en) 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
JP4570809B2 (ja) 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 積層型半導体装置及びその製造方法
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6327168B1 (en) * 2000-10-19 2001-12-04 Motorola, Inc. Single-source or single-destination signal routing through identical electronics module
CN1159725C (zh) * 2000-11-28 2004-07-28 Agc科技股份有限公司 可扩充存储器的集成电路装置
JP2002359346A (ja) 2001-05-30 2002-12-13 Sharp Corp 半導体装置および半導体チップの積層方法
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
KR100435813B1 (ko) * 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
US7081373B2 (en) 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
US6635970B2 (en) * 2002-02-06 2003-10-21 International Business Machines Corporation Power distribution design method for stacked flip-chip packages
US7049691B2 (en) 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
JP3908146B2 (ja) 2002-10-28 2007-04-25 シャープ株式会社 半導体装置及び積層型半導体装置
KR100497111B1 (ko) 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
KR20040087501A (ko) 2003-04-08 2004-10-14 삼성전자주식회사 센터 패드 반도체 칩의 패키지 및 그 제조방법
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
TWI225292B (en) 2003-04-23 2004-12-11 Advanced Semiconductor Eng Multi-chips stacked package
US6853064B2 (en) 2003-05-12 2005-02-08 Micron Technology, Inc. Semiconductor component having stacked, encapsulated dice
KR100626364B1 (ko) 2003-07-02 2006-09-20 삼성전자주식회사 멀티칩을 내장한 반도체패키지
TWI229434B (en) 2003-08-25 2005-03-11 Advanced Semiconductor Eng Flip chip stacked package
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
JP3880572B2 (ja) 2003-10-31 2007-02-14 沖電気工業株式会社 半導体チップ及び半導体装置
JP4205553B2 (ja) 2003-11-06 2009-01-07 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
KR100621992B1 (ko) * 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
DE102004060345A1 (de) 2003-12-26 2005-10-06 Elpida Memory, Inc. Halbleitervorrichtung mit geschichteten Chips
JP4068616B2 (ja) * 2003-12-26 2008-03-26 エルピーダメモリ株式会社 半導体装置
US7282791B2 (en) 2004-07-09 2007-10-16 Elpida Memory, Inc. Stacked semiconductor device and semiconductor memory module
DE102004049356B4 (de) 2004-10-08 2006-06-29 Infineon Technologies Ag Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben
CN1763771A (zh) * 2004-10-20 2006-04-26 菘凯科技股份有限公司 记忆卡结构及其制造方法
US7215031B2 (en) 2004-11-10 2007-05-08 Oki Electric Industry Co., Ltd. Multi chip package
US7217995B2 (en) 2004-11-12 2007-05-15 Macronix International Co., Ltd. Apparatus for stacking electrical components using insulated and interconnecting via
JP4309368B2 (ja) * 2005-03-30 2009-08-05 エルピーダメモリ株式会社 半導体記憶装置
JP4423453B2 (ja) * 2005-05-25 2010-03-03 エルピーダメモリ株式会社 半導体記憶装置
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
JP4507101B2 (ja) * 2005-06-30 2010-07-21 エルピーダメモリ株式会社 半導体記憶装置及びその製造方法
US7269067B2 (en) * 2005-07-06 2007-09-11 Spansion Llc Programming a memory device
KR100729356B1 (ko) * 2005-08-23 2007-06-15 삼성전자주식회사 플래시 메모리 장치의 레이아웃 구조
KR100630761B1 (ko) 2005-08-23 2006-10-02 삼성전자주식회사 메모리 집적도가 다른 2개의 반도체 메모리 칩들을내장하는 반도체 멀티칩 패키지
DE112006002300B4 (de) * 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US20070165457A1 (en) 2005-09-30 2007-07-19 Jin-Ki Kim Nonvolatile memory system
US7629675B2 (en) 2006-05-03 2009-12-08 Marvell International Technology Ltd. System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices
US7561457B2 (en) * 2006-08-18 2009-07-14 Spansion Llc Select transistor using buried bit line from core
US7817470B2 (en) * 2006-11-27 2010-10-19 Mosaid Technologies Incorporated Non-volatile memory serial core architecture
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
US7494846B2 (en) * 2007-03-09 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Design techniques for stacking identical memory dies
JP2008300469A (ja) * 2007-05-30 2008-12-11 Sharp Corp 不揮発性半導体記憶装置
JP2009003991A (ja) * 2007-06-19 2009-01-08 Toshiba Corp 半導体装置及び半導体メモリテスト装置
JP5149554B2 (ja) * 2007-07-17 2013-02-20 株式会社日立製作所 半導体装置
DE102007036989B4 (de) 2007-08-06 2015-02-26 Qimonda Ag Verfahren zum Betrieb einer Speichervorrichtung, Speichereinrichtung und Speichervorrichtung
US7623365B2 (en) * 2007-08-29 2009-11-24 Micron Technology, Inc. Memory device interface methods, apparatus, and systems
WO2009055003A1 (en) * 2007-10-22 2009-04-30 Pargman Steven R Portable digital photograph albums and methods for providing the same
US9251899B2 (en) 2008-02-12 2016-02-02 Virident Systems, Inc. Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers
KR101393311B1 (ko) * 2008-03-19 2014-05-12 삼성전자주식회사 프로세스 변화량을 보상하는 멀티 칩 패키지 메모리
US8031505B2 (en) * 2008-07-25 2011-10-04 Samsung Electronics Co., Ltd. Stacked memory module and system
US7796446B2 (en) * 2008-09-19 2010-09-14 Qimonda Ag Memory dies for flexible use and method for configuring memory dies
US7894230B2 (en) * 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150087343A (ko) * 2012-11-19 2015-07-29 실리콘 스토리지 테크놀로지 인크 3차원 플래시 메모리 시스템
US9472284B2 (en) 2012-11-19 2016-10-18 Silicon Storage Technology, Inc. Three-dimensional flash memory system
US9767923B2 (en) 2012-11-19 2017-09-19 Silicon Storage Technology, Inc. Three-dimensional flash memory system
KR20190084854A (ko) * 2018-01-09 2019-07-17 윈본드 일렉트로닉스 코포레이션 반도체 기억장치

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