JP2012518859A - マスタデバイスを含む積み重ね半導体デバイス - Google Patents

マスタデバイスを含む積み重ね半導体デバイス Download PDF

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Publication number
JP2012518859A
JP2012518859A JP2011550388A JP2011550388A JP2012518859A JP 2012518859 A JP2012518859 A JP 2012518859A JP 2011550388 A JP2011550388 A JP 2011550388A JP 2011550388 A JP2011550388 A JP 2011550388A JP 2012518859 A JP2012518859 A JP 2012518859A
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chip
volatile memory
area
memory chip
additional
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JP2011550388A
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Japanese (ja)
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JP2012518859A5 (enExample
Inventor
ジン−キ・キム
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Mosaid Technologies Inc
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Conversant Intellectual Property Management Inc
Mosaid Technologies Inc
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Publication of JP2012518859A publication Critical patent/JP2012518859A/ja
Publication of JP2012518859A5 publication Critical patent/JP2012518859A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2011550388A 2009-02-24 2010-02-12 マスタデバイスを含む積み重ね半導体デバイス Pending JP2012518859A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15491009P 2009-02-24 2009-02-24
US61/154,910 2009-02-24
US12/429,310 2009-04-24
US12/429,310 US7894230B2 (en) 2009-02-24 2009-04-24 Stacked semiconductor devices including a master device
PCT/CA2010/000195 WO2010096901A1 (en) 2009-02-24 2010-02-12 Stacked semiconductor devices including a master device

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JP2013214655A Division JP2014057077A (ja) 2009-02-24 2013-10-15 マスタデバイスを含む積み重ね半導体デバイス

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JP2012518859A true JP2012518859A (ja) 2012-08-16
JP2012518859A5 JP2012518859A5 (enExample) 2013-03-14

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JP2011550388A Pending JP2012518859A (ja) 2009-02-24 2010-02-12 マスタデバイスを含む積み重ね半導体デバイス
JP2013214655A Pending JP2014057077A (ja) 2009-02-24 2013-10-15 マスタデバイスを含む積み重ね半導体デバイス

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US (4) US7894230B2 (enExample)
EP (1) EP2401745A1 (enExample)
JP (2) JP2012518859A (enExample)
KR (1) KR20110121671A (enExample)
CN (2) CN104332179A (enExample)
DE (1) DE112010000880T5 (enExample)
TW (1) TW201101464A (enExample)
WO (1) WO2010096901A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
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JP2014501016A (ja) * 2010-11-23 2014-01-16 モサイド・テクノロジーズ・インコーポレーテッド 集積回路デバイス内の内部電源を共有するための方法および装置
JP2016504701A (ja) * 2012-11-19 2016-02-12 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 三次元フラッシュメモリシステム
JP2016528719A (ja) * 2013-06-26 2016-09-15 インテル・コーポレーション マルチダイアセンブリにおける電力管理
JP2017502444A (ja) * 2013-12-02 2017-01-19 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 構成可能なピンを備える三次元フラッシュｎｏｒメモリシステム

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WO2010047140A1 (ja) * 2008-10-20 2010-04-29 国立大学法人東京大学 集積回路装置
US7894230B2 (en) * 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device
US20100332177A1 (en) * 2009-06-30 2010-12-30 National Tsing Hua University Test access control apparatus and method thereof
KR20110052133A (ko) * 2009-11-12 2011-05-18 주식회사 하이닉스반도체 반도체 장치
US8159075B2 (en) * 2009-12-18 2012-04-17 United Microelectronics Corp. Semiconductor chip stack and manufacturing method thereof
KR101046273B1 (ko) * 2010-01-29 2011-07-04 주식회사 하이닉스반도체 반도체 장치
US20110272788A1 (en) * 2010-05-10 2011-11-10 International Business Machines Corporation Computer system wafer integrating different dies in stacked master-slave structures
KR101085724B1 (ko) * 2010-05-10 2011-11-21 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 동작 방법
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
KR101854251B1 (ko) 2010-11-30 2018-05-03 삼성전자주식회사 멀티 채널 반도체 메모리 장치 및 그를 구비하는 반도체 장치
JP2012146377A (ja) * 2011-01-14 2012-08-02 Elpida Memory Inc 半導体装置
JP5647026B2 (ja) * 2011-02-02 2014-12-24 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
US9432298B1 (en) 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
KR20120122549A (ko) 2011-04-29 2012-11-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 리페어 방법
US10141314B2 (en) * 2011-05-04 2018-11-27 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
DE112011106009T5 (de) * 2011-12-23 2014-12-18 Intel Corp. Getrennte Mikrokanal-Spannungsdomänen in Stapelspeicherarchitektur
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