KR20100069595A - Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법 - Google Patents

Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법 Download PDF

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Publication number
KR20100069595A
KR20100069595A KR1020090123832A KR20090123832A KR20100069595A KR 20100069595 A KR20100069595 A KR 20100069595A KR 1020090123832 A KR1020090123832 A KR 1020090123832A KR 20090123832 A KR20090123832 A KR 20090123832A KR 20100069595 A KR20100069595 A KR 20100069595A
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South Korea
Prior art keywords
laser light
single crystal
substrate
crystal semiconductor
semiconductor layer
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KR1020090123832A
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English (en)
Korean (ko)
Inventor
히데토 오누마
준페이 모모
šœ페이 야마자키
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Publication of KR20100069595A publication Critical patent/KR20100069595A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3458—Monocrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
KR1020090123832A 2008-12-15 2009-12-14 Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법 Ceased KR20100069595A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008318377 2008-12-15
JPJP-P-2008-318377 2008-12-15

Related Child Applications (1)

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KR1020160128549A Division KR20160120266A (ko) 2008-12-15 2016-10-05 Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법

Publications (1)

Publication Number Publication Date
KR20100069595A true KR20100069595A (ko) 2010-06-24

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KR1020090123832A Ceased KR20100069595A (ko) 2008-12-15 2009-12-14 Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법
KR1020160128549A Ceased KR20160120266A (ko) 2008-12-15 2016-10-05 Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법

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KR1020160128549A Ceased KR20160120266A (ko) 2008-12-15 2016-10-05 Ｓｏｉ 기판의 제작 방법, 반도체 장치의 제작 방법

Country Status (5)

Country Link
US (1) US8394703B2 (enExample)
JP (1) JP5610759B2 (enExample)
KR (2) KR20100069595A (enExample)
CN (1) CN101752294B (enExample)
SG (2) SG162675A1 (enExample)

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FR2972564B1 (fr) * 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
TWI664731B (zh) * 2013-05-20 2019-07-01 半導體能源研究所股份有限公司 半導體裝置
US9425063B2 (en) * 2014-06-19 2016-08-23 Infineon Technologies Ag Method of reducing an impurity concentration in a semiconductor body, method of manufacturing a semiconductor device and semiconductor device
KR102524983B1 (ko) 2014-11-28 2023-04-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 모듈, 및 전자 기기
JP6850096B2 (ja) * 2015-09-24 2021-03-31 株式会社半導体エネルギー研究所 半導体装置の作製方法及び電子機器の作製方法
US10026843B2 (en) 2015-11-30 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structure of semiconductor device, manufacturing method thereof, and manufacturing method of active region of semiconductor device
US11255606B2 (en) * 2015-12-30 2022-02-22 Mattson Technology, Inc. Gas flow control for millisecond anneal system
JP6579086B2 (ja) * 2016-11-15 2019-09-25 信越半導体株式会社 デバイス形成方法
JP2020508564A (ja) * 2017-02-21 2020-03-19 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板を接合する方法および装置
KR102791109B1 (ko) 2019-06-14 2025-04-07 삼성전자주식회사 집적 회로 반도체 소자의 제조 방법

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JPH1140501A (ja) * 1997-05-20 1999-02-12 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
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Also Published As

Publication number Publication date
JP5610759B2 (ja) 2014-10-22
SG182208A1 (en) 2012-07-30
US20100151663A1 (en) 2010-06-17
CN101752294A (zh) 2010-06-23
CN101752294B (zh) 2015-02-25
SG162675A1 (en) 2010-07-29
US8394703B2 (en) 2013-03-12
JP2010166035A (ja) 2010-07-29
KR20160120266A (ko) 2016-10-17

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