KR20060050794A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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Publication number
KR20060050794A
KR20060050794A KR1020050079848A KR20050079848A KR20060050794A KR 20060050794 A KR20060050794 A KR 20060050794A KR 1020050079848 A KR1020050079848 A KR 1020050079848A KR 20050079848 A KR20050079848 A KR 20050079848A KR 20060050794 A KR20060050794 A KR 20060050794A
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KR
South Korea
Prior art keywords
substrate
bump
electrodes
elasticity
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020050079848A
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English (en)
Korean (ko)
Inventor
다다또모 스가
토시히로 이토
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
다다또모 스가
오끼 덴끼 고오교 가부시끼가이샤
산요덴키가부시키가이샤
샤프 가부시키가이샤
닛폰 덴키 가부시키가이샤
로무 가부시키가이샤
소니 가부시끼 가이샤
가부시끼가이샤 도시바
후지쯔 가부시끼가이샤
마쓰시타 덴키 산교 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 르네사스 테크놀로지, 다다또모 스가, 오끼 덴끼 고오교 가부시끼가이샤, 산요덴키가부시키가이샤, 샤프 가부시키가이샤, 닛폰 덴키 가부시키가이샤, 로무 가부시키가이샤, 소니 가부시끼 가이샤, 가부시끼가이샤 도시바, 후지쯔 가부시끼가이샤, 마쓰시타 덴키 산교 가부시끼 가이샤 filed Critical 가부시끼가이샤 르네사스 테크놀로지
Publication of KR20060050794A publication Critical patent/KR20060050794A/ko
Ceased legal-status Critical Current

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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
KR1020050079848A 2004-08-30 2005-08-30 반도체 장치 및 그 제조방법 Ceased KR20060050794A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2004-00250453 2004-08-30
JP2004250453A JP4050732B2 (ja) 2004-08-30 2004-08-30 半導体装置およびその製造方法

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KR1020060118387A Division KR100821574B1 (ko) 2004-08-30 2006-11-28 반도체 장치의 제조방법

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KR20060050794A true KR20060050794A (ko) 2006-05-19

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KR1020050079848A Ceased KR20060050794A (ko) 2004-08-30 2005-08-30 반도체 장치 및 그 제조방법
KR1020060118387A Expired - Fee Related KR100821574B1 (ko) 2004-08-30 2006-11-28 반도체 장치의 제조방법

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US (2) US7268430B2 (enExample)
JP (1) JP4050732B2 (enExample)
KR (2) KR20060050794A (enExample)
CN (1) CN100437995C (enExample)
TW (1) TWI297185B (enExample)

Families Citing this family (32)

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Publication number Priority date Publication date Assignee Title
CN100468674C (zh) * 2004-11-25 2009-03-11 日本电气株式会社 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
US7786588B2 (en) * 2006-01-31 2010-08-31 International Business Machines Corporation Composite interconnect structure using injection molded solder technique
WO2008041484A1 (fr) * 2006-09-26 2008-04-10 Alps Electric Co., Ltd. Contact élastique et procédé de liage entre des bornes métalliques l'utilisant
JP2008124355A (ja) * 2006-11-15 2008-05-29 Epson Imaging Devices Corp 半導体装置、異方性導電材、実装構造体、電気光学装置、突起電極の製造方法、異方性導電材の製造方法、及び、電子機器
US7793819B2 (en) * 2007-03-19 2010-09-14 Infineon Technologies Ag Apparatus and method for connecting a component with a substrate
US20080315388A1 (en) * 2007-06-22 2008-12-25 Shanggar Periaman Vertical controlled side chip connection for 3d processor package
JP4992604B2 (ja) * 2007-08-15 2012-08-08 株式会社ニコン 接合装置、接合方法
JP4548459B2 (ja) * 2007-08-21 2010-09-22 セイコーエプソン株式会社 電子部品の実装構造体
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
JP5228479B2 (ja) * 2007-12-28 2013-07-03 富士通株式会社 電子装置の製造方法
JP5493399B2 (ja) * 2009-03-12 2014-05-14 株式会社ニコン 製造装置、及び、半導体装置の製造方法
WO2010106878A1 (ja) * 2009-03-18 2010-09-23 コニカミノルタホールディングス株式会社 熱電変換素子
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