KR20050120280A - 웨이퍼 레벨 칩 스택 패키지 제조 방법 - Google Patents

웨이퍼 레벨 칩 스택 패키지 제조 방법 Download PDF

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Publication number
KR20050120280A
KR20050120280A KR1020040045567A KR20040045567A KR20050120280A KR 20050120280 A KR20050120280 A KR 20050120280A KR 1020040045567 A KR1020040045567 A KR 1020040045567A KR 20040045567 A KR20040045567 A KR 20040045567A KR 20050120280 A KR20050120280 A KR 20050120280A
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South Korea
Prior art keywords
stack package
chip
chip stack
wafer level
wafer
Prior art date
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KR1020040045567A
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English (en)
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KR100570514B1 (ko
Inventor
김순범
김웅광
이강욱
정세영
심성민
송영희
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삼성전자주식회사
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Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020040045567A priority Critical patent/KR100570514B1/ko
Priority to US11/038,210 priority patent/US7151009B2/en
Publication of KR20050120280A publication Critical patent/KR20050120280A/ko
Application granted granted Critical
Publication of KR100570514B1 publication Critical patent/KR100570514B1/ko
Priority to US11/703,900 priority patent/US20070200216A1/en

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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/3511—Warping

Abstract

본 발명은 웨이퍼 레벨 칩 스택 패키지 제조 방법에 관한 것으로서, ⒜칩 가장자리 부분에 관통전극이 형성되고 그 관통전극의 일측 부분에 범프가 형성된 반도체 칩 복수 개를 갖는 웨이퍼들을 준비하는 단계, ⒝칩 단위로 고상 접착수단을 부착하는 단계, ⒞상하 반도체 칩들간 서로 대응되는 관통전극을 범프 본딩시키고 상기 고상 접착수단에 의해 상하 반도체 칩들이 부착되도록 하여 복수의 웨이퍼를 적층시키는 단계, ⒟적층된 웨이퍼들을 칩 스택 패키지 단위로 절단하는 단계, 및 ⒠칩 스택 패키지의 반도체 칩들 사이의 공간에 액상 접착수단을 주입하는 단계를 포함하는 것을 특징으로 한다. 이에 따르면, 웨이퍼 레벨이나 칩 레벨 등에서의 칩 적층 과정에서 물리적인 또는 기계적인 안전성이 확보될 수 있으며 신뢰성이 확보될 수 있다. 또한, 칩 적층 후 범프 연결에 대한 검사도 가능하게 된다.

Description

웨이퍼 레벨 칩 스택 패키지 제조 방법{Manufacturing method for wafer level chip stack package}
본 발명은 칩 스택 패키지 제조 방법에 관한 것으로서, 더욱 상세하게는 웨이퍼 제조 공정(Wafer Fabrication) 단계에서 칩 적층이 이루어져 제조되는 웨이퍼 레벨 칩 스택 패키지(wafer level chip stack package)에 관한 것이다.
최근 반도체 산업의 발전과 사용자의 요구에 따라 전자기기는 더욱 더 소형화 및 경량화 되고 있으며 전자기기의 핵심 부품인 반도체 칩 패키지 또한 소형화 및 경량화 되고 있다. 이와 같은 추세에 따라 개발된 반도체 칩 패키지의 한 형태로서 복수의 반도체 칩이 수직으로 적층된 형태로 기판에 실장되어 하나의 단위 반도체 칩 패키지로 구현된 칩 스택 패키지(Chip Stack Package)가 알려져 있다. 칩 스택 패키지는 하나의 반도체 칩을 내재하는 단위 반도체 칩 패키지 복수 개를 이용하는 것보다 크기나 무게 및 실장 면적에 있어서 소형화와 경량화에 유리한 장점을 갖는다. 일반적으로 스택 칩 패키지는 칩 레벨(chip level)에서 제조되나 최근에는 웨이퍼 레벨(wafer level)에서 제조가 이루어지고 있다.
통상적으로 웨이퍼 레벨 칩 스택 패키지는 재배선 등에 의해 반도체 칩의 전극패드와 연결된 관통전극이 칩 가장자리에 형성된 구조를 갖는 복수의 반도체 칩들이 범프 접합에 의해 수직으로 적층된 구조이다. 상하 반도체 칩간 관통전극이 범프로 접합됨으로써 물리적인 결합과 전기적인 연결이 동시에 이루어진다.
그런데, 이와 같은 일반적인 웨이퍼 레벨 칩 스택 패키지의 경우 범프 본딩에 의해 적층이 이루어지기 때문에 칩과 칩 사이에 빈 공간이 발생된다. 이 칩과 칩 사이의 빈 공간은 칩 스택 패키지의 기계적 강도를 저해하고 신뢰성 불량을 유발시키는 원인이 된다. 따라서, 칩과 칩 사이의 빈 공간을 채워주는 것이 필요하다. 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에서는 칩과 칩 사이의 빈 공간을 채워주기 위한 방안으로서 액상의 접착제나 접착 테이프를 이용하는 방법이 잘 알려져 있다.
도 1은 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 일 예에 의해 제조된 웨이퍼 레벨 칩 스택 패키지를 나타낸 단면도이다.
도 1에 도시된 웨이퍼 레벨 칩 스택 패키지(130)는, 웨이퍼 준비 단계와, 웨이퍼 적층 단계와, 웨이퍼 소잉 단계, 및 액상 접착제 주입 단계를 포함하는 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에 의해 제조된다.
먼저, 반도체 칩(111)의 가장자리 부분에서 그 반도체 칩(111)을 관통하여 관통전극(113)이 형성되어 있고 그 관통전극(113)에 범프(117)가 형성된 구조를 갖는 반도체 칩(111) 복수 개가 형성된 웨이퍼(도시안됨, 이하 동일)들을 준비한다. 여기서, 범프(117)를 형성하지 않고 관통전극(113)이 반도체 칩(111)으로부터 일정 길이 돌출되도록 형성하여 범프 역할을 하도록 하는 것도 가능하다.
다음으로, 수직으로 대응되는 반도체 칩(111)들이 범프(117)와 관통전극(113)의 상호 접합에 의해 적층되도록 웨이퍼 복수 개를 수직으로 적층시킨다. 범프(117)에 의해 상하 반도체 칩들(111)은 전기적으로 연결된다.
다음으로, 적층된 웨이퍼에 대한 소잉을 진행하여 각 칩 스택 패키지(130) 단위로 절단한다.
다음으로, 반도체 칩(111)들 사이의 빈 공간에 액상 접착제(123)를 주입한다.
전술한 바와 같은 웨이퍼 레벨 칩 스택 패키지 제조 방법은 칩과 칩 사이의 빈 공간에 액상 접착제가 채워지기 때문에 칩과 칩 사이의 공간이 비어 있는 웨이퍼 레벨 칩 스택 패키지의 경우보다 기계적 강도가 우수하고 신뢰성이 향상된다.
그러나, 액상 접착제를 이용하는 웨이퍼 레벨 칩 스택 방법은 액상 접착제가 갖는 흐름성과 액상 접착제 성분으로 포함되어 있는 금속 또는 비금속 재질의 필러(filler) 조각의 크기가 매우 큼으로 인하여 칩과 칩 사이의 빈 공간에 완전히 채워지지 못하고 도 1에서 참조 부호 135에 의해 지시되는 빈 공간이 발생되는 단점이 있었다. 이와 같은 문제를 해결하기 위해 접착 테이프를 이용하는 웨이퍼 레벨 칩 스택 패키지 제조 방법이 제안되었다.
도 2는 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 다른 예에 의해 제조된 웨이퍼 레벨 칩 스택 패키지를 나타낸 단면도이다.
도 2에 도시된 웨이퍼 레벨 칩 스택 패키지(230)는 웨이퍼 준비 단계와, 접착 테이프 부착 단계, 웨이퍼 적층 단계, 및 웨이퍼 소잉 단계를 포함하는 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에 의해 제조된다.
먼저 반도체 칩(211)의 가장자리 부분에서 그 반도체 칩(211)을 관통하여 관통전극(213)이 형성되어 있고 그 관통전극(213)에 범프(217)가 형성된 구조를 갖는 반도체 칩 복수 개가 형성된 웨이퍼(도시안됨, 이하 동일)들을 준비한다.
다음으로, 웨이퍼 상태에서 각 반도체 칩(211)에 범프(213)를 피하여 접착 테이프(221)를 부착한다.
다음으로 범프(217)와 관통전극(213)이 접합되어 전기적인 연결이 이루어지도록 복수의 웨이퍼를 수직으로 적층한다.
다음으로, 적층된 웨이퍼에 대한 소잉을 진행하여 각 칩 스택 패키지(230) 단위로 절단한다.
이와 같은 웨이퍼 레벨 칩 스택 패키지 제조 방법은 액상 접착제를 사용하는 경우보다 칩과 칩 사이의 빈 공간이 확실하게 채워질 수 있고 물리적인 강도 면에서 우수하다. 그러나, 접착 테이프를 사용하는 웨이퍼 레벨 칩 스택 패키지 제조 방법은 접착 테이프를 사용하기 때문에 칩 두께가 매우 얇은 경우 칩 스택 과정에서 가해지는 압력에 의해 반도체 칩의 가장자리 부분이 들리는 등의 이유로 반도체 칩이 휘는 경우가 발생될 수 있고, 적층 과정에서 측면으로 접착 테이프의 접착제 성분이 도 2의 224번과 같이 흘러 내리는 등 칩 적층이 저해될 수 있다. 따라서, 2개 이상의 칩 스택에서는 적합하지 않다.
본 발명의 목적은 상기한 바와 같은 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 문제점들을 극복하기 위한 방안으로서, 기계적 강도 및 신뢰성을 동시에 향상시킬 수 있는 웨이퍼 레벨 칩 스택 패키지 제조 방법을 제공하는 데에 있다.
이와 같은 목적을 달성하기 위한 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법은, ⒜칩 가장자리 부분에 관통전극이 형성되고 그 관통전극이 형성된 반도체 칩 복수 개를 갖는 웨이퍼들을 준비하는 단계, ⒝칩 단위로 고상 접착수단을 부착하는 단계, ⒞상하 반도체 칩들간 서로 대응되는 관통전극을 범프 본딩시키고 상기 고상 접착수단에 의해 상하 반도체 칩들이 부착되도록 하여 복수의 웨이퍼를 적층시키는 단계, ⒟적층된 웨이퍼들을 칩 스택 패키지 단위로 절단하는 단계, 및 ⒠칩 스택 패키지의 반도체 칩들 사이의 공간에 액상 접착수단을 주입하는 단계를 포함하는 것을 특징으로 한다.
본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에 있어서, 상기 고상 접착수단은 베이스 필름의 양면에 접착층이 형성된 접착 테이프인 것이 바람직하다.
본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에 있어서, 상기 반도체 칩들 사이의 거리가 10~50㎛인 것이 바람직하다.
본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에 있어서, 상기 ⒜단계 후에 적층된 웨이퍼들을 기판에 실장하는 단계를 포함할 수 있다.
본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법에 있어서, 상기 ⒜단계에서 상기 고상 접착수단은 범프로부터 소정 거리 이격되어 범프 안쪽에 형성되는 것이 바람직하다.
이하 첨부 도면을 참조하여 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법을 보다 상세하게 설명하고자 한다.
도 3a내지 도 3f는 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 일 실시예에 의한 공정 진행 상태를 나타낸 단면도이다.
본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법은 웨이퍼 준비 단계, 고상 접착 수단 부착 단계, 웨이퍼 적층 단계, 절단 단계, 및 액상 접착수단 주입단계를 포함한다.
먼저, 도 3a에서와 같이 반도체 칩(11)의 가장자리 부분에서 그 반도체 칩(11)을 관통하여 관통전극(13)이 형성되고 그 관통전극(13)의 일측 말단 부분에 범프(17)가 형성된 웨이퍼(10)를 복수 개 준비한다. 관통전극(13)은 도시되지 않았지만 재배선 패턴 등에 의해 반도체 칩(11) 내부의 집적회로와 연결되어 칩 외부와의 전기적인 연결을 위하여 제공된다. 여기서, 범프(117)를 형성하지 않고 관통전극(13)을 반도체 칩(11)으로부터 돌출되도록 형성하여 관통전극(13)간에 범프 접합이 일어나도록 하는 것도 가능하다. 범프(17)로서는 다양한 형태를 가질 수 있으며 여기서는 볼 형태의 범프를 갖도록 하고 있다. 범프의 재질로서는 잘 알려진 바와 같이 솔더, 니켈, 금, 구리 등 전기 전도성과 접합성이 우수한 다양한 재질이 사용될 수 있다.
다음으로, 도 3b에서와 같이 웨이퍼 상태에서 각 반도체 칩(11)에 범프(17)의 안쪽에 위치하도록 하여 고상 접착수단, 예컨대 접착 테이프(21)를 부착한다. 여기서, 접착 테이프(21)는 베이스 필름의 양면에 접착층이 형성된 것이 바람직하나 이에 한정되는 것은 아니다. 접착 테이프(21)는 범프(17)로부터 소정 거리만큼 떨어진 위치에 형성되도록 하여 범프(17)에 영향을 주지 않도록 한다.
다음으로, 도 3c에서와 같이 상하 반도체 칩들(11)간에 범프(17)와 관통전극(13)이 접합되도록 하여 웨이퍼(10) 복수 개를 수직으로 적층한다. 상하 반도체 칩(11)들이 범프(17)에 의해 물리적인 결합이 이루어짐과 동시에 전기적인 상호 연결이 이루어진다. 더불어, 접착 테이프(21)에 의해 반도체 칩(11)들이 서로 부착된다. 이에 따라, 웨이퍼 적층 과정을 포함하여 제조 과정에서 반도체 칩(11)에 가해지는 물리적인 충격 또는 기계적인 충격 등을 접착 테이프(21)가 완화시킬 수 있다.
다음으로, 도 3d에서와 같이 적층된 웨이퍼(10)들을 각 칩 스택 칩 패키지 단위로 절단한다. 고속 회전되는 다이아몬드 블레이드(diamond blade)(50)로 스크라이브 라인(scribe line)(15)을 절단하여 각 스택 칩 패키지 단위로 절단이 이루어질 수 있다. 여기서, 다이아몬드 블레이드(50) 대신에 레이저 빔에 의해 절단하는 것도 가능하다.
다음으로, 도 3e에서와 같이 반도체 칩(11)들 사이의 빈 공간에 액상 접착제(23)를 주입한다. 접착 테이프(21)의 외측의 반도체 칩(11)들 사이의 공간에 범프(17)를 둘러싸도록 액상 접착제(23)가 채워진다. 액상 접착제(23)로는 에폭시 수지 접착제가 바람직하다. 여기서, 액상 접착제(23)의 주입은 반도체 칩(11)들 사이의 공간 측방에서 액상 접착제(23)가 도포되는 형태로 주입될 수 있다. 모세관 현상에 의해 액상 접착제(23)가 접착 테이프(21)에 접촉이 이루어지며 범프(17)를 감싸게 된다.
다음으로, 사용된 액상 접착제(23)에 대한 경화 공정 등을 거치면 도 3f에서와 같이 웨이퍼 레벨 칩 스택 패키지(30)의 제조가 완료된다.
전술한 실시예에서와 같은 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법은 칩과 칩 사이에 빈 공간이 고형 접착수단과 액상 접착수단으로 완전히 채워진 구조를 갖게 된다. 칩 중앙 부분에 고형 접착수단이 형성되어 있기 때문에 액상 접착수단은 칩 중앙까지 주입될 필요가 없다. 따라서, 액상 접착수단이 주입되는 경로의 길이가 짧아져 반도체 칩들 사이의 폭이 30㎛이하의 미세한 공간일 경우에도 종래 사용되는 액상 접착제를 이용하여 채워줄 수 있게 된다. 바람직하게는 반도체 칩들 사이의 폭이 10~50㎛인 경우에 적용할 수 있다.
도 4는 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 다른 실시예에 의해 제조된 웨이퍼 레벨 칩 스택 패키지를 나타낸 단면도이다.
도 4에 도시된 웨이퍼 레벨 칩 스택 패키지(70)는 상기한 웨이퍼 레벨 칩 스케일 패키지 제조 방법의 실시예에서의 웨이퍼 적층 단계에서 최하위의 웨이퍼(10)를 기판(41)에 실장하는 단계를 포함하도록 함으로써 제조될 수 있다. 또는 전술한 웨이퍼 레벨 칩 스케일 패키지 제조 방법의 실시예에서 최종 단계 후에 기판(41)을 부착하는 단계를 진행하여 얻어질 수 있다. 반도체 칩(11)과 기판 패드(43)가 범프 본딩에 의해 접합이 이루어지고 반도체 칩(11)과 기판(41)간에 접착 테이프(21)에 의해 결합이 이루어진다. 후속 공정으로 기판(41)에 대한 범프(45)의 형성으로 기판(41)을 포함하는 웨이퍼 레벨 칩 스택 패키지(70)가 얻어질 수 있다.
한편, 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법은 전술한 실시예에 한정되지 않고 본 발명의 기술적 중심 사상을 벗어나지 않는 범위 내에서 다양한 변형 실시가 가능하다. 예를 들어, 칩 레벨에서 플립 칩 본딩에 의한 적층 구조를 갖는 칩 스택 패키지의 제조에도 적용이 가능하다. 그리고, 웨이퍼들 사이나, 반도체 칩들 사이, 반도체 칩과 기판 사이에 공간이 형성되는 구조의 반도체 장치의 제조에 적용되어 기계적 강도 및 신뢰성 확보를 위하여 적용될 수 있다.
이상과 같은 본 발명에 의한 웨이퍼 레벨 칩 스택 패키지 제조 방법에 따르면, 웨이퍼 레벨이나 칩 레벨 등에서의 칩 적층 과정에서 물리적인 또는 기계적인 안전성이 확보될 수 있으며 신뢰성이 확보될 수 있다. 또한, 칩 적층 후 범프 연결에 대한 검사도 가능하게 된다.
도 1은 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 일 예에 의해 제조된 웨이퍼 레벨 칩 스택 패키지를 나타낸 단면도이다.
도 2는 종래 기술에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 다른 예에 의해 제조된 웨이퍼 레벨 칩 스택 패키지를 나타낸 단면도이다.
도 3a내지 도 3f는 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 일 실시예에 의한 공정 진행 상태를 나타낸 단면도이다.
도 4는 본 발명에 따른 웨이퍼 레벨 칩 스택 패키지 제조 방법의 다른 실시예에 의해 제조된 웨이퍼 레벨 칩 스택 패키지를 나타낸 단면도이다.
* 도면의 주요 부분에 대한 부호의 설명 *
10; 웨이퍼 11; 반도체 칩
13; 관통전극 15; 스크라이브 라인
17; 범프 21; 접착 테이프
23; 액상 접착제 30; 칩 스택 패키지
41; 기판 43; 기판 패드

Claims (5)

  1. ⒜칩 가장자리 부분에 관통전극이 형성되고 그 관통전극의 일측 부분에 범프가 형성된 반도체 칩 복수 개를 갖는 웨이퍼들을 준비하는 단계,
    ⒝칩 단위로 고상 접착수단을 부착하는 단계,
    ⒞상하 반도체 칩들간 서로 대응되는 관통전극을 범프 본딩시키고 상기 고상 접착수단에 의해 상하 반도체 칩들이 부착되도록 하여 복수의 웨이퍼를 적층시키는 단계,
    ⒟적층된 웨이퍼들을 칩 스택 패키지 단위로 절단하는 단계, 및
    ⒠칩 스택 패키지의 반도체 칩들 사이의 공간에 액상 접착수단을 주입하는 단계
    를 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스택 패키지 제조 방법.
  2. 제 1항에 있어서,
    상기 고상 접착수단은 베이스 필름의 양면에 접착층이 형성된 접착 테이프인 것을 특징으로 하는 웨이퍼 레벨 칩 스택 패키지 제조 방법.
  3. 제 1항에 있어서,
    상기 반도체 칩들 사이의 거리가 10~50㎛인 것을 특징으로 하는 웨이퍼 레벨 칩 스택 패키지 제조 방법.
  4. 제 1항에 있어서,
    상기 ⒜단계 후에 적층된 웨이퍼들을 기판에 실장하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스택 패키지 제조 방법.
  5. 제 1항에 있어서,
    상기 ⒜단계에서 상기 고상 접착수단은 상기 범프로부터 소정 거리 이격되어 범프 안쪽에 형성되는 것을 특징으로 하는 웨이퍼 레벨 칩 스택 패키지 제조 방법.
KR1020040045567A 2004-06-18 2004-06-18 웨이퍼 레벨 칩 스택 패키지 제조 방법 KR100570514B1 (ko)

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US11/038,210 US7151009B2 (en) 2004-06-18 2005-01-21 Method for manufacturing wafer level chip stack package
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CN111081648B (zh) * 2018-10-18 2023-08-22 爱思开海力士有限公司 包括支承上芯片层叠物的支承块的半导体封装件

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