JP2009094451A - 耐クラック性半導体パッケージ及びその製造方法 - Google Patents
耐クラック性半導体パッケージ及びその製造方法 Download PDFInfo
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L2924/14—Integrated circuits
Abstract
【解決手段】集積回路部220を含む半導体基板と、上記半導体基板の集積回路部220周辺に少なくとも局部的に形成され、上記半導体基板とは異なる異種物質が充填されているクラック伝播防止部270を含む半導体パッケージ200を提供する。また、集積回路部220を含む半導体基板の上記集積回路部220周辺に少なくとも局部的にトレンチを形成して、該トレンチに上記半導体基板とは異なる異種物質を充填する工程を含む半導体パッケージ200の製造方法を提供する。また、後続実装工程で、クラック(Crack)やチッピング(chipping)などの不良率を下げて収率を高めることで、全体の製造コストを節減することができる。
【選択図】図2
Description
210:基板
220:集積回路部
225:電極端子
230、232:誘電層
240:再配置導電層
250:下部金属層
260:ソルダバンプ
270:クラック伝播防止部
300:支持部材
400:クラック伝播防止部
Claims (20)
- 集積回路部を含む半導体基板と、
該半導体基板の集積回路部周辺に少なくとも局部的に形成されて、前記半導体基板とは異なる異種物質が充填されているクラック伝播防止部とを含む半導体パッケージ。 - 前記クラック伝播防止部が、前記半導体基板を垂直的に貫通するトレンチに基板材質と異なる異種物質が充填されている請求項1に記載の半導体パッケージ。
- 前記トレンチが、垂直断面の幅が相異するように形成されている請求項2に記載の半導体パッケージ。
- 前記クラック伝播防止部が、前記集積回路部のエッジ部分を局部的にカバーする請求項1に記載の半導体パッケージ。
- 前記集積回路部上面に形成されて外部との電気的接続のためのソルダバンプを含む請求項1に記載の半導体パッケージ。
- 前記集積回路部の電極端子と前記ソルダバンプと間を電気的に接続する再配置導電層を含む請求項5に記載の半導体パッケージ。
- 前記クラック伝播防止部が、エポキシ樹脂で形成される請求項1に記載の半導体パッケージ。
- 前記クラック伝播防止部が、前記半導体基板の上面及び下面に露出している請求項1に記載の半導体パッケージ。
- 集積回路部を含む半導体基板と、
該半導体基板の集積回路部を露出させたまま基板の側面及び下面をカバーして、前記半導体基板とは異なる異種物質で構成されたクラック伝播防止部とを含む半導体パッケージ。 - 集積回路部を含む半導体基板の前記集積回路部周辺に少なくとも局部的にトレンチを形成して、該トレンチに前記半導体基板とは異なる異種物質を充填する工程を含む半導体パッケージ製造方法。
- 前記トレンチを、半導体基板を乾式蝕刻、湿式蝕刻、または部分的な切断によって形成する請求項10に記載の半導体パッケージ製造方法。
- 前記トレンチの垂直断面の幅を相異するように形成する請求項10に記載の半導体パッケージ製造方法。
- 前記トレンチ内部に充填される異種物質が、エポキシ樹脂である請求項10に記載の半導体パッケージ製造方法。
- 前記トレンチ内部を充填した後、前記半導体基板の下面を薄型化する工程をさらに含む請求項10に記載の半導体パッケージ製造方法。
- 前記集積回路部上面に電極端子と電気的に接続する再配置導電層を形成する工程と、
該再配置導電層の一端と電気的に接続するソルダバンプを形成する工程とをさらに含む請求項10に記載の半導体パッケージ製造方法。 - 前記トレンチ内部を充填した後、前記半導体基板を集積回路部単位で切断する工程をさらに含む請求項10に記載の半導体パッケージ製造方法。
- 複数の集積回路部を含む半導体基板の単位素子別切断ライン近くにトレンチを形成して、前記半導体基板の下面を薄型化させて前記トレンチを露出させて、前記半導体基板の下面及び前記トレンチに前記半導体基板と異なる物質を形成して、前記半導体基板を集積回路部単位で切断する工程を含む半導体パッケージ製造方法。
- 前記半導体基板の薄型化が、前記半導体基板の集積回路部が形成された面に支持部材を付着した後、前記半導体基板のもう一方の面を研削して薄型化させることを特徴とする請求項17に記載の半導体パッケージ製造方法。
- 前記半導体基板の下面及び前記トレンチに前記半導体基板と異なる物質を形成する工程が、樹脂物質をディスフェンシング、コーティング、またはプリンティングによって形成されることを特徴とする請求項17に記載の半導体パッケージ製造方法。
- 前記半導体基板の切断前に半導体基板の下面を薄型化させて基板下面に形成された物質を除去する工程をさらに含む請求項17に記載の半導体パッケージ製造方法。
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KR1020070101343A KR100887479B1 (ko) | 2007-10-09 | 2007-10-09 | 내균열성 반도체 패키지 및 그 제조 방법 |
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US (1) | US7919833B2 (ja) |
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Cited By (1)
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JP2013511155A (ja) * | 2009-11-17 | 2013-03-28 | クリー インコーポレイテッド | クラックストップを備えたデバイス |
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KR100986544B1 (ko) * | 2009-06-10 | 2010-10-07 | 엘지이노텍 주식회사 | 반도체 발광소자 및 그 제조방법 |
JP2012195388A (ja) * | 2011-03-15 | 2012-10-11 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
US9184138B2 (en) | 2011-12-29 | 2015-11-10 | Stmicroelectronics (Grenoble 2) Sas | Semiconductor integrated device with mechanically decoupled active area and related manufacturing process |
US9496195B2 (en) * | 2012-10-02 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP |
US9620413B2 (en) | 2012-10-02 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
KR101971202B1 (ko) * | 2012-11-22 | 2019-04-23 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 그 제조방법 |
US9704824B2 (en) | 2013-01-03 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming embedded wafer level chip scale packages |
US9721862B2 (en) | 2013-01-03 | 2017-08-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages |
US10141202B2 (en) | 2013-05-20 | 2018-11-27 | Qualcomm Incorporated | Semiconductor device comprising mold for top side and sidewall protection |
US9379065B2 (en) * | 2013-08-16 | 2016-06-28 | Qualcomm Incorporated | Crack stopping structure in wafer level packaging (WLP) |
TWI658543B (zh) * | 2013-12-05 | 2019-05-01 | 新加坡商史達晶片有限公司 | 在半導體封裝中使用標準化載體的半導體裝置及方法 |
US9508623B2 (en) * | 2014-06-08 | 2016-11-29 | UTAC Headquarters Pte. Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
TWI555145B (zh) * | 2014-12-31 | 2016-10-21 | 矽品精密工業股份有限公司 | 基板結構 |
JP2018170333A (ja) * | 2017-03-29 | 2018-11-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN107611095A (zh) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体(江阴)有限公司 | 晶圆级芯片封装结构及其制备方法 |
KR20220090664A (ko) | 2020-12-22 | 2022-06-30 | 삼성전자주식회사 | 스트립 기판 및 반도체 패키지 |
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US7919833B2 (en) | 2011-04-05 |
KR100887479B1 (ko) | 2009-03-10 |
TW200917442A (en) | 2009-04-16 |
TWI358111B (en) | 2012-02-11 |
US20090091001A1 (en) | 2009-04-09 |
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