KR102415206B1 - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR102415206B1 KR102415206B1 KR1020160080257A KR20160080257A KR102415206B1 KR 102415206 B1 KR102415206 B1 KR 102415206B1 KR 1020160080257 A KR1020160080257 A KR 1020160080257A KR 20160080257 A KR20160080257 A KR 20160080257A KR 102415206 B1 KR102415206 B1 KR 102415206B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H01L27/11526—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L27/11573—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020160080257A KR102415206B1 (ko) | 2016-06-27 | 2016-06-27 | 반도체 장치 |
US15/349,518 US9853051B1 (en) | 2016-06-27 | 2016-11-11 | Semiconductor device and method of manufacturing the same |
CN201611129796.6A CN107546229B (zh) | 2016-06-27 | 2016-12-09 | 半导体装置及其制造方法 |
CN202010623869.7A CN111952310A (zh) | 2016-06-27 | 2016-12-09 | 半导体装置及其制造方法 |
US15/812,404 US10930666B2 (en) | 2016-06-27 | 2017-11-14 | Semiconductor device and method of manufacturing the same |
US17/153,610 US20210143178A1 (en) | 2016-06-27 | 2021-01-20 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020160080257A KR102415206B1 (ko) | 2016-06-27 | 2016-06-27 | 반도체 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20180001301A KR20180001301A (ko) | 2018-01-04 |
KR102415206B1 true KR102415206B1 (ko) | 2022-07-01 |
Family
ID=60674719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020160080257A KR102415206B1 (ko) | 2016-06-27 | 2016-06-27 | 반도체 장치 |
Country Status (3)
Country | Link |
---|---|
US (3) | US9853051B1 (zh) |
KR (1) | KR102415206B1 (zh) |
CN (2) | CN107546229B (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102415206B1 (ko) * | 2016-06-27 | 2022-07-01 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR102442933B1 (ko) * | 2017-08-21 | 2022-09-15 | 삼성전자주식회사 | 3차원 반도체 장치 |
KR20200047882A (ko) | 2018-10-25 | 2020-05-08 | 삼성전자주식회사 | 3차원 반도체 소자 |
CN114141781A (zh) * | 2019-01-31 | 2022-03-04 | 长江存储科技有限责任公司 | 三维存储器件中的阶梯形成 |
JP7132142B2 (ja) * | 2019-02-05 | 2022-09-06 | キオクシア株式会社 | 半導体記憶装置の製造方法 |
KR20200110052A (ko) | 2019-03-15 | 2020-09-23 | 에스케이하이닉스 주식회사 | 수직형 반도체장치 및 그 제조 방법 |
KR20200110072A (ko) | 2019-03-15 | 2020-09-23 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 제조방법 |
KR20200114285A (ko) * | 2019-03-28 | 2020-10-07 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
KR20210012331A (ko) | 2019-07-24 | 2021-02-03 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 제조방법 |
KR20210036144A (ko) * | 2019-09-25 | 2021-04-02 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
KR20210109808A (ko) | 2020-02-28 | 2021-09-07 | 삼성전자주식회사 | 수직형 메모리 소자 |
CN114586153A (zh) | 2020-03-23 | 2022-06-03 | 长江存储科技有限责任公司 | 在三维存储器件中的阶梯结构及用于形成其的方法 |
EP3931870B1 (en) * | 2020-03-23 | 2024-05-15 | Yangtze Memory Technologies Co., Ltd. | Staircase structure in three-dimensional memory device and method for forming the same |
WO2021189189A1 (en) * | 2020-03-23 | 2021-09-30 | Yangtze Memory Technologies Co., Ltd. | Staircase structure in three-dimensional memory device and method for forming the same |
KR20220076989A (ko) | 2020-12-01 | 2022-06-08 | 에스케이하이닉스 주식회사 | 반도체 장치의 제조 방법 |
US20220328512A1 (en) * | 2021-04-09 | 2022-10-13 | Sandisk Technologies Llc | Three-dimensional memory device with off-center or reverse slope staircase regions and methods for forming the same |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
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US7915667B2 (en) * | 2008-06-11 | 2011-03-29 | Qimonda Ag | Integrated circuits having a contact region and methods for manufacturing the same |
KR20110042619A (ko) * | 2009-10-19 | 2011-04-27 | 삼성전자주식회사 | 3차원 반도체 장치 및 그 제조 방법 |
KR20110108216A (ko) * | 2010-03-26 | 2011-10-05 | 삼성전자주식회사 | 3차원 반도체 장치 |
KR20120030815A (ko) * | 2010-09-20 | 2012-03-29 | 삼성전자주식회사 | 3차원 반도체 장치 및 그 제조 방법 |
CN102915955B (zh) * | 2011-08-04 | 2016-09-07 | 三星电子株式会社 | 半导体器件及其制造方法 |
KR101325492B1 (ko) * | 2012-02-24 | 2013-11-07 | 서울대학교산학협력단 | 3차원 스타구조를 갖는 낸드 플래시 메모리 어레이 및 그 동작방법 |
KR20140008622A (ko) * | 2012-07-10 | 2014-01-22 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102003529B1 (ko) * | 2012-08-22 | 2019-07-25 | 삼성전자주식회사 | 적층된 전극들을 형성하는 방법 및 이를 이용하여 제조되는 3차원 반도체 장치 |
KR101936846B1 (ko) | 2012-10-24 | 2019-01-11 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조방법 |
KR20140063147A (ko) | 2012-11-16 | 2014-05-27 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR20140075340A (ko) * | 2012-12-11 | 2014-06-19 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
JP2014187176A (ja) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR20150073251A (ko) * | 2013-12-20 | 2015-07-01 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102183713B1 (ko) * | 2014-02-13 | 2020-11-26 | 삼성전자주식회사 | 3차원 반도체 장치의 계단형 연결 구조 및 이를 형성하는 방법 |
KR102134912B1 (ko) * | 2014-03-21 | 2020-07-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR102282138B1 (ko) * | 2014-12-09 | 2021-07-27 | 삼성전자주식회사 | 반도체 소자 |
KR102310511B1 (ko) * | 2014-12-19 | 2021-10-08 | 삼성전자주식회사 | 반도체 소자 및 그 형성 방법 |
US20160293625A1 (en) * | 2015-03-31 | 2016-10-06 | Joo-Heon Kang | Three Dimensional Semiconductor Memory Devices and Methods of Fabricating the Same |
KR102392685B1 (ko) * | 2015-07-06 | 2022-04-29 | 삼성전자주식회사 | 배선 구조체를 갖는 반도체 소자 |
US10373970B2 (en) * | 2016-03-02 | 2019-08-06 | Micron Technology, Inc. | Semiconductor device structures including staircase structures, and related methods and electronic systems |
US9941209B2 (en) * | 2016-03-11 | 2018-04-10 | Micron Technology, Inc. | Conductive structures, systems and devices including conductive structures and related methods |
KR102415206B1 (ko) * | 2016-06-27 | 2022-07-01 | 에스케이하이닉스 주식회사 | 반도체 장치 |
-
2016
- 2016-06-27 KR KR1020160080257A patent/KR102415206B1/ko active IP Right Grant
- 2016-11-11 US US15/349,518 patent/US9853051B1/en active Active
- 2016-12-09 CN CN201611129796.6A patent/CN107546229B/zh active Active
- 2016-12-09 CN CN202010623869.7A patent/CN111952310A/zh active Pending
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2017
- 2017-11-14 US US15/812,404 patent/US10930666B2/en active Active
-
2021
- 2021-01-20 US US17/153,610 patent/US20210143178A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
CN111952310A (zh) | 2020-11-17 |
US20180069021A1 (en) | 2018-03-08 |
US10930666B2 (en) | 2021-02-23 |
US9853051B1 (en) | 2017-12-26 |
US20210143178A1 (en) | 2021-05-13 |
KR20180001301A (ko) | 2018-01-04 |
CN107546229A (zh) | 2018-01-05 |
US20170373088A1 (en) | 2017-12-28 |
CN107546229B (zh) | 2020-07-14 |
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