JP7132142B2 - 半導体記憶装置の製造方法 - Google Patents
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Description
Claims (1)
- 基板上に、第1層と第2層の組からなる単位層を複数積層して積層体を形成し、
最上層からn層(nは2以上の整数)までの前記単位層を加工して、メモリセルアレイ形成領域から離れる第1方向に向かって降段していくa段(aは1以上n以下の整数)の段差を有する降段段差群、および前記第1方向に向かって昇段していくa段の段差を有する昇段段差群を形成し、
第1領域の前記降段段差群並びに前記第1領域に隣接する第2領域の前記降段段差群および前記昇段段差群に対して、前記第1領域の前記昇段段差群がn層の単位層分低くなるように前記積層体を加工する半導体記憶装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019018384A JP7132142B2 (ja) | 2019-02-05 | 2019-02-05 | 半導体記憶装置の製造方法 |
US16/529,970 US11296108B2 (en) | 2019-02-05 | 2019-08-02 | Semiconductor memory device and manufacturing method of semiconductor memory device |
TW108128689A TWI709229B (zh) | 2019-02-05 | 2019-08-13 | 半導體記憶裝置及其製造方法 |
CN201910748426.8A CN111524898B (zh) | 2019-02-05 | 2019-08-14 | 半导体存储装置及其制造方法 |
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JP2019018384A JP7132142B2 (ja) | 2019-02-05 | 2019-02-05 | 半導体記憶装置の製造方法 |
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JP2020126928A JP2020126928A (ja) | 2020-08-20 |
JP7132142B2 true JP7132142B2 (ja) | 2022-09-06 |
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JP2019018384A Active JP7132142B2 (ja) | 2019-02-05 | 2019-02-05 | 半導体記憶装置の製造方法 |
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US (1) | US11296108B2 (ja) |
JP (1) | JP7132142B2 (ja) |
CN (1) | CN111524898B (ja) |
TW (1) | TWI709229B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN109952644A (zh) | 2019-01-31 | 2019-06-28 | 长江存储科技有限责任公司 | 三维存储器件中的阶梯形成 |
US11825654B2 (en) * | 2020-12-07 | 2023-11-21 | Macronix International Co., Ltd. | Memory device |
KR20220083115A (ko) * | 2020-12-11 | 2022-06-20 | 에스케이하이닉스 주식회사 | 3차원 메모리 장치 및 그 제조방법 |
JP2022134606A (ja) * | 2021-03-03 | 2022-09-15 | キオクシア株式会社 | 半導体記憶装置およびその製造方法 |
US11961801B2 (en) | 2021-07-12 | 2024-04-16 | Micron Technology, Inc. | Integrated circuitry, memory circuitry comprising strings of memory cells, and method of forming integrated circuitry |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258458A (ja) | 2007-04-06 | 2008-10-23 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
US20160111361A1 (en) | 2014-10-17 | 2016-04-21 | SK Hynix Inc. | 3d nonvolatile memory device |
US20170317088A1 (en) | 2016-05-02 | 2017-11-02 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
US20170373088A1 (en) | 2016-06-27 | 2017-12-28 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011124593A (ja) * | 2011-01-26 | 2011-06-23 | Oki Semiconductor Co Ltd | 半導体装置 |
KR20130072522A (ko) * | 2011-12-22 | 2013-07-02 | 에스케이하이닉스 주식회사 | 3차원 불휘발성 메모리 소자 및 그 제조 방법 |
US10038073B1 (en) * | 2012-04-09 | 2018-07-31 | Monolithic 3D Inc. | 3D integrated circuit device |
US9595533B2 (en) * | 2012-08-30 | 2017-03-14 | Micron Technology, Inc. | Memory array having connections going through control gates |
KR101974352B1 (ko) * | 2012-12-07 | 2019-05-02 | 삼성전자주식회사 | 수직 셀을 갖는 반도체 소자의 제조 방법 및 그에 의해 제조된 반도체 소자 |
KR102046504B1 (ko) | 2013-01-17 | 2019-11-19 | 삼성전자주식회사 | 수직형 반도체 소자의 패드 구조물 및 배선 구조물 |
KR20160096309A (ko) * | 2015-02-05 | 2016-08-16 | 에스케이하이닉스 주식회사 | 3차원 비휘발성 반도체 장치 |
KR20170014757A (ko) * | 2015-07-31 | 2017-02-08 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
US10186520B2 (en) * | 2015-09-11 | 2019-01-22 | Toshiba Memory Corporation | Semiconductor memory devices including a memory cell array and stepped wiring portions, and manufacturing methods thereof |
TWI572018B (zh) * | 2015-10-28 | 2017-02-21 | 旺宏電子股份有限公司 | 記憶體元件及其製作方法 |
KR102568886B1 (ko) | 2015-11-16 | 2023-08-22 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR102536261B1 (ko) | 2015-12-18 | 2023-05-25 | 삼성전자주식회사 | 3차원 반도체 장치 |
US10373970B2 (en) * | 2016-03-02 | 2019-08-06 | Micron Technology, Inc. | Semiconductor device structures including staircase structures, and related methods and electronic systems |
US9905514B2 (en) * | 2016-04-11 | 2018-02-27 | Micron Technology, Inc. | Semiconductor device structures including staircase structures, and related methods and electronic systems |
JP2018037513A (ja) | 2016-08-31 | 2018-03-08 | 東芝メモリ株式会社 | 半導体装置 |
JP2018152419A (ja) * | 2017-03-10 | 2018-09-27 | 東芝メモリ株式会社 | 半導体記憶装置 |
TWI630709B (zh) | 2017-03-14 | 2018-07-21 | 旺宏電子股份有限公司 | 三維半導體元件及其製造方法 |
KR102416028B1 (ko) * | 2017-04-07 | 2022-07-04 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
KR102421766B1 (ko) * | 2017-07-07 | 2022-07-18 | 삼성전자주식회사 | 3차원 반도체 장치 및 그 제조 방법 |
KR102427324B1 (ko) * | 2017-07-25 | 2022-07-29 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
CN109300902A (zh) * | 2018-09-28 | 2019-02-01 | 长江存储科技有限责任公司 | 3d存储器件 |
KR20200047882A (ko) * | 2018-10-25 | 2020-05-08 | 삼성전자주식회사 | 3차원 반도체 소자 |
KR20200088680A (ko) * | 2019-01-15 | 2020-07-23 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
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2019
- 2019-02-05 JP JP2019018384A patent/JP7132142B2/ja active Active
- 2019-08-02 US US16/529,970 patent/US11296108B2/en active Active
- 2019-08-13 TW TW108128689A patent/TWI709229B/zh active
- 2019-08-14 CN CN201910748426.8A patent/CN111524898B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258458A (ja) | 2007-04-06 | 2008-10-23 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
US20160111361A1 (en) | 2014-10-17 | 2016-04-21 | SK Hynix Inc. | 3d nonvolatile memory device |
US20170317088A1 (en) | 2016-05-02 | 2017-11-02 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
US20170373088A1 (en) | 2016-06-27 | 2017-12-28 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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TWI709229B (zh) | 2020-11-01 |
CN111524898A (zh) | 2020-08-11 |
US11296108B2 (en) | 2022-04-05 |
CN111524898B (zh) | 2023-10-27 |
US20200251491A1 (en) | 2020-08-06 |
JP2020126928A (ja) | 2020-08-20 |
TW202030872A (zh) | 2020-08-16 |
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