KR101764686B1 - 배선 기판, 그 제조 방법, 및 반도체 패키지 - Google Patents

배선 기판, 그 제조 방법, 및 반도체 패키지 Download PDF

Info

Publication number
KR101764686B1
KR101764686B1 KR1020110000067A KR20110000067A KR101764686B1 KR 101764686 B1 KR101764686 B1 KR 101764686B1 KR 1020110000067 A KR1020110000067 A KR 1020110000067A KR 20110000067 A KR20110000067 A KR 20110000067A KR 101764686 B1 KR101764686 B1 KR 101764686B1
Authority
KR
South Korea
Prior art keywords
layer
insulating layer
wiring
alignment mark
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020110000067A
Other languages
English (en)
Korean (ko)
Other versions
KR20110083506A (ko
Inventor
준이치 나카무라
가즈히로 고바야시
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20110083506A publication Critical patent/KR20110083506A/ko
Application granted granted Critical
Publication of KR101764686B1 publication Critical patent/KR101764686B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1152—Replicating the surface structure of a sacrificial layer, e.g. for roughening
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7408—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including alignment aids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
KR1020110000067A 2010-01-13 2011-01-03 배선 기판, 그 제조 방법, 및 반도체 패키지 Active KR101764686B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010005017A JP5603600B2 (ja) 2010-01-13 2010-01-13 配線基板及びその製造方法、並びに半導体パッケージ
JPJP-P-2010-005017 2010-01-13

Publications (2)

Publication Number Publication Date
KR20110083506A KR20110083506A (ko) 2011-07-20
KR101764686B1 true KR101764686B1 (ko) 2017-08-03

Family

ID=44257911

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110000067A Active KR101764686B1 (ko) 2010-01-13 2011-01-03 배선 기판, 그 제조 방법, 및 반도체 패키지

Country Status (4)

Country Link
US (2) US8525356B2 (https=)
JP (1) JP5603600B2 (https=)
KR (1) KR101764686B1 (https=)
TW (1) TWI500373B (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5590985B2 (ja) * 2010-06-21 2014-09-17 新光電気工業株式会社 半導体装置及びその製造方法
US8802554B2 (en) * 2011-02-15 2014-08-12 Marvell World Trade Ltd. Patterns of passivation material on bond pads and methods of manufacture thereof
US10074600B2 (en) 2012-03-30 2018-09-11 Ati Technologies Ulc Method of manufacturing interposer-based damping resistor
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US9596765B2 (en) * 2012-09-11 2017-03-14 Meiko Electronics Co., Ltd. Manufacturing method for component incorporated substrate and component incorporated substrate manufactured using the method
JP6092555B2 (ja) * 2012-09-24 2017-03-08 新光電気工業株式会社 配線基板の製造方法
US9035194B2 (en) * 2012-10-30 2015-05-19 Intel Corporation Circuit board with integrated passive devices
US20140167900A1 (en) 2012-12-14 2014-06-19 Gregorio R. Murtagian Surface-mount inductor structures for forming one or more inductors with substrate traces
US9165878B2 (en) * 2013-03-14 2015-10-20 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP6291738B2 (ja) * 2013-07-25 2018-03-14 富士通株式会社 回路基板、回路基板の製造方法及び電子機器
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
DE102013218404A1 (de) * 2013-09-13 2015-03-19 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zu seiner Herstellung
KR20150064445A (ko) * 2013-12-03 2015-06-11 삼성전기주식회사 반도체 패키지용 코어리스 기판 및 그 제조 방법, 이를 이용한 반도체 패키지 제조 방법
CN104701185B (zh) * 2013-12-06 2018-01-02 碁鼎科技秦皇岛有限公司 封装基板、封装结构以及封装基板的制作方法
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9679841B2 (en) * 2014-05-13 2017-06-13 Qualcomm Incorporated Substrate and method of forming the same
JP2016039290A (ja) * 2014-08-08 2016-03-22 イビデン株式会社 プリント配線板および半導体パッケージ
JP2016039302A (ja) * 2014-08-08 2016-03-22 イビデン株式会社 プリント配線板とその製造方法および半導体パッケージ
JP5795415B1 (ja) * 2014-08-29 2015-10-14 新光電気工業株式会社 配線基板及びその製造方法
JP6510884B2 (ja) * 2015-05-19 2019-05-08 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
US9691699B2 (en) * 2015-11-03 2017-06-27 Unimicron Technology Corp. Circuit structure and method for manufacturing the same
KR102534940B1 (ko) * 2016-07-28 2023-05-22 삼성전기주식회사 인쇄회로기판
JP7271081B2 (ja) * 2017-10-18 2023-05-11 日東電工株式会社 配線回路基板
US10147721B1 (en) 2017-12-20 2018-12-04 Advanced Micro Devices, Inc. Method and apparatus for dynamic calibration of on-die-precision-resistors
JP7448309B2 (ja) * 2018-11-27 2024-03-12 日東電工株式会社 配線回路基板およびその製造方法
JP2020202205A (ja) * 2019-06-06 2020-12-17 イビデン株式会社 プリント配線板とプリント配線板の製造方法
WO2021112499A1 (ko) 2019-12-04 2021-06-10 엘지이노텍 주식회사 인쇄회로기판
JP2022047385A (ja) * 2020-09-11 2022-03-24 キオクシア株式会社 プリント配線基板およびメモリシステム
JP7216139B2 (ja) * 2021-04-20 2023-01-31 Ｆｉｃｔ株式会社 回路基板の製造方法
TWI771229B (zh) * 2021-11-18 2022-07-11 恆勁科技股份有限公司 半導體封裝載板及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176232A (ja) * 2000-09-29 2002-06-21 Sumitomo Bakelite Co Ltd アライメントマーク
JP2002198462A (ja) * 2000-10-18 2002-07-12 Nec Corp 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ
JP2009033183A (ja) * 2008-09-01 2009-02-12 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835950A (ja) * 1981-08-28 1983-03-02 Hitachi Ltd 半導体装置
JPS59134840A (ja) * 1982-12-02 1984-08-02 Stanley Electric Co Ltd オ−ミツク接続された金属電極の像および位置を照明により検知する方法およびシステム
JPH078447B2 (ja) * 1987-08-06 1995-02-01 株式会社神戸製鋼所 薄板加工用ドリル
JPH03268316A (ja) * 1990-03-16 1991-11-29 Fujitsu Ltd 半導体装置の製造方法
US5627110A (en) * 1994-10-24 1997-05-06 Advanced Micro Devices, Inc. Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used
JP3855320B2 (ja) 1996-10-16 2006-12-06 株式会社トッパンＮｅｃサーキットソリューションズ 半導体装置用基板の製造方法及び半導体装置の製造方法
KR20000057687A (ko) * 1996-12-19 2000-09-25 엔도 마사루 프린트 배선판 및 그 제조방법
US5898227A (en) * 1997-02-18 1999-04-27 International Business Machines Corporation Alignment targets having enhanced contrast
US6156243A (en) * 1997-04-25 2000-12-05 Hoya Corporation Mold and method of producing the same
JPH1140908A (ja) 1997-07-22 1999-02-12 Ibiden Co Ltd プリント配線板
CN100426491C (zh) * 1997-10-17 2008-10-15 揖斐电株式会社 封装基板
WO1999034654A1 (en) * 1997-12-29 1999-07-08 Ibiden Co., Ltd. Multilayer printed wiring board
KR100906931B1 (ko) * 1998-02-26 2009-07-10 이비덴 가부시키가이샤 필드 바이어 구조를 갖는 다층프린트 배선판
JP2004047898A (ja) * 2002-07-15 2004-02-12 Sumitomo Bakelite Co Ltd プリント配線板の製造方法及び多層プリント配線板の製造方法
JP3987781B2 (ja) * 2002-09-30 2007-10-10 日本特殊陶業株式会社 配線基板の製造方法
JP2004200187A (ja) * 2002-12-16 2004-07-15 Nikon Corp プリント配線板
US20050067378A1 (en) * 2003-09-30 2005-03-31 Harry Fuerhaupter Method for micro-roughening treatment of copper and mixed-metal circuitry
US8119920B2 (en) * 2004-02-04 2012-02-21 Ibiden Co., Ltd. Multilayer printed wiring board
JP2006186321A (ja) * 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法
JP2006216711A (ja) * 2005-02-02 2006-08-17 Ibiden Co Ltd 多層プリント配線板
JP4768994B2 (ja) * 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 配線基板および半導体装置
JP2006278929A (ja) * 2005-03-30 2006-10-12 Shinko Electric Ind Co Ltd フレキシブル回路基板の製造方法
TWI294678B (en) * 2006-04-19 2008-03-11 Phoenix Prec Technology Corp A method for manufacturing a coreless package substrate
US7911038B2 (en) * 2006-06-30 2011-03-22 Renesas Electronics Corporation Wiring board, semiconductor device using wiring board and their manufacturing methods
JP5214139B2 (ja) * 2006-12-04 2013-06-19 新光電気工業株式会社 配線基板及びその製造方法
JP2008258520A (ja) * 2007-04-09 2008-10-23 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板
JP2009194321A (ja) * 2008-02-18 2009-08-27 Shinko Electric Ind Co Ltd 配線基板及びその製造方法、半導体パッケージ
JP5203108B2 (ja) * 2008-09-12 2013-06-05 新光電気工業株式会社 配線基板及びその製造方法
US8365402B2 (en) * 2008-09-30 2013-02-05 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP5561460B2 (ja) * 2009-06-03 2014-07-30 新光電気工業株式会社 配線基板および配線基板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176232A (ja) * 2000-09-29 2002-06-21 Sumitomo Bakelite Co Ltd アライメントマーク
JP2002198462A (ja) * 2000-10-18 2002-07-12 Nec Corp 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ
JP2009033183A (ja) * 2008-09-01 2009-02-12 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板

Also Published As

Publication number Publication date
KR20110083506A (ko) 2011-07-20
US8673744B2 (en) 2014-03-18
JP2011146477A (ja) 2011-07-28
US8525356B2 (en) 2013-09-03
TWI500373B (zh) 2015-09-11
JP5603600B2 (ja) 2014-10-08
TW201136481A (en) 2011-10-16
US20110169164A1 (en) 2011-07-14
US20130269185A1 (en) 2013-10-17

Similar Documents

Publication Publication Date Title
KR101764686B1 (ko) 배선 기판, 그 제조 방법, 및 반도체 패키지
US8973259B2 (en) Method for manufacturing a multilayered circuit board
CN101683004B (zh) 多层印刷线路板的制造方法
US20110010932A1 (en) Wiring board, semiconductor device having wiring board, and method of manufacturing wiring board
US8780572B2 (en) Printed circuit board having electronic component
US20130328212A1 (en) Semiconductor package and manufacturing method thereof
KR101811923B1 (ko) 배선 기판
JP7074409B2 (ja) 素子内蔵型印刷回路基板
US9334576B2 (en) Wiring substrate and method of manufacturing wiring substrate
JP2013118255A (ja) 配線基板及びその製造方法、半導体パッケージ
TWI676409B (zh) 用於製造電子模組的方法及電子模組
US8785786B2 (en) Wiring board and method of manufacturing the same
TW201503771A (zh) 配線基板
US20120152606A1 (en) Printed wiring board
JP2012142557A (ja) 配線基板及びその製造方法
US8756804B2 (en) Method of manufacturing printed circuit board
US20150156882A1 (en) Printed circuit board, manufacturing method thereof, and semiconductor package
TW201419956A (zh) 配線基板
KR20120007444A (ko) 인쇄회로기판 및 그 제조방법
KR20120022363A (ko) 반도체 패키지 기판 및 그 제조방법
KR101044154B1 (ko) 절연층 아래로 매립된 최외각 회로층을 갖는 인쇄회로기판 및 그 제조방법
KR20100104932A (ko) 인쇄회로기판의 제조방법
TWI461134B (zh) 載板結構及其製作方法
KR20110131040A (ko) 매립형 인쇄회로기판 및 그 제조방법
KR101730468B1 (ko) 범프가 포함된 인쇄회로기판 및 그 제조방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

PE0801 Dismissal of amendment

St.27 status event code: A-2-2-P10-P12-nap-PE0801

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20200630

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20210629

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20220615

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000