KR101139302B1 - 리버스 톤 공정을 사용하는 리세스형 구조물 형성 방법 - Google Patents
리버스 톤 공정을 사용하는 리세스형 구조물 형성 방법 Download PDFInfo
- Publication number
- KR101139302B1 KR101139302B1 KR1020067024158A KR20067024158A KR101139302B1 KR 101139302 B1 KR101139302 B1 KR 101139302B1 KR 1020067024158 A KR1020067024158 A KR 1020067024158A KR 20067024158 A KR20067024158 A KR 20067024158A KR 101139302 B1 KR101139302 B1 KR 101139302B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- shape
- multilayer structure
- forming
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
- B81C1/0046—Surface micromachining, i.e. structuring layers on the substrate using stamping, e.g. imprinting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/091—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts by printing or stamping
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US85087604A | 2004-05-21 | 2004-05-21 | |
| US10/850,876 | 2004-05-21 | ||
| US10/946,570 US7186656B2 (en) | 2004-05-21 | 2004-09-21 | Method of forming a recessed structure employing a reverse tone process |
| US10/946,570 | 2004-09-21 | ||
| PCT/US2005/017756 WO2005114719A2 (en) | 2004-05-21 | 2005-05-19 | Method of forming a recessed structure employing a reverse tone process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070013305A KR20070013305A (ko) | 2007-01-30 |
| KR101139302B1 true KR101139302B1 (ko) | 2012-05-25 |
Family
ID=35429090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020067024158A Expired - Fee Related KR101139302B1 (ko) | 2004-05-21 | 2005-05-19 | 리버스 톤 공정을 사용하는 리세스형 구조물 형성 방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7186656B2 (https=) |
| EP (1) | EP1761949A4 (https=) |
| JP (2) | JP5059608B2 (https=) |
| KR (1) | KR101139302B1 (https=) |
| CN (1) | CN101356303B (https=) |
| TW (1) | TWI289326B (https=) |
| WO (1) | WO2005114719A2 (https=) |
Families Citing this family (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| US7396475B2 (en) * | 2003-04-25 | 2008-07-08 | Molecular Imprints, Inc. | Method of forming stepped structures employing imprint lithography |
| US7906180B2 (en) | 2004-02-27 | 2011-03-15 | Molecular Imprints, Inc. | Composition for an etching mask comprising a silicon-containing material |
| US7384569B1 (en) * | 2004-08-02 | 2008-06-10 | Advanced Micro Devices, Inc. | Imprint lithography mask trimming for imprint mask using etch |
| US7252777B2 (en) * | 2004-09-21 | 2007-08-07 | Molecular Imprints, Inc. | Method of forming an in-situ recessed structure |
| US7547504B2 (en) * | 2004-09-21 | 2009-06-16 | Molecular Imprints, Inc. | Pattern reversal employing thick residual layers |
| US7205244B2 (en) | 2004-09-21 | 2007-04-17 | Molecular Imprints | Patterning substrates employing multi-film layers defining etch-differential interfaces |
| US7585424B2 (en) * | 2005-01-18 | 2009-09-08 | Hewlett-Packard Development Company, L.P. | Pattern reversal process for self aligned imprint lithography and device |
| JP4247198B2 (ja) * | 2005-03-31 | 2009-04-02 | 株式会社東芝 | 半導体装置の製造方法 |
| US7482280B2 (en) * | 2005-08-15 | 2009-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a lithography pattern |
| US20070077763A1 (en) * | 2005-09-30 | 2007-04-05 | Molecular Imprints, Inc. | Deposition technique to planarize a multi-layer structure |
| US7767570B2 (en) * | 2006-03-22 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US7759253B2 (en) * | 2006-08-07 | 2010-07-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and material for forming a double exposure lithography pattern |
| US7776628B2 (en) * | 2006-11-16 | 2010-08-17 | International Business Machines Corporation | Method and system for tone inverting of residual layer tolerant imprint lithography |
| WO2008157640A2 (en) | 2007-06-18 | 2008-12-24 | Illumina, Inc. | Microfabrication methods for the optimal patterning of substrates |
| US8136224B1 (en) | 2008-05-15 | 2012-03-20 | Western Digital (Fremont), Llc | Method and system for providing a perpendicular magnetic recording head utilizing a mask having an undercut line |
| KR101541439B1 (ko) * | 2008-07-24 | 2015-08-03 | 닛산 가가쿠 고교 가부시키 가이샤 | 코팅 조성물 및 패턴 형성방법 |
| US8415010B2 (en) * | 2008-10-20 | 2013-04-09 | Molecular Imprints, Inc. | Nano-imprint lithography stack with enhanced adhesion between silicon-containing and non-silicon containing layers |
| US8529778B2 (en) * | 2008-11-13 | 2013-09-10 | Molecular Imprints, Inc. | Large area patterning of nano-sized shapes |
| SG174889A1 (en) * | 2009-03-23 | 2011-11-28 | Intevac Inc | A process for optimization of island to trench ratio in patterned media |
| US8492009B1 (en) | 2009-08-25 | 2013-07-23 | Wd Media, Inc. | Electrochemical etching of magnetic recording layer |
| NL2007161A (en) | 2010-09-09 | 2012-03-12 | Asml Netherlands Bv | Lithography using self-assembled polymers. |
| EP2635419B1 (en) | 2010-11-05 | 2020-06-17 | Molecular Imprints, Inc. | Patterning of non-convex shaped nanostructures |
| EP2718465B1 (en) | 2011-06-09 | 2022-04-13 | Illumina, Inc. | Method of making an analyte array |
| CA2856163C (en) | 2011-10-28 | 2019-05-07 | Illumina, Inc. | Microarray fabrication system and method |
| US8870345B2 (en) * | 2012-07-16 | 2014-10-28 | Xerox Corporation | Method of making superoleophobic re-entrant resist structures |
| KR20140046266A (ko) * | 2012-10-10 | 2014-04-18 | 삼성디스플레이 주식회사 | 패턴 형성 장치, 패턴 형성 장치의 제조 방법 및 패턴 형성 방법 |
| US9105295B2 (en) * | 2013-02-25 | 2015-08-11 | HGST Netherlands B.V. | Pattern tone reversal |
| JP6496320B2 (ja) | 2013-12-30 | 2019-04-03 | キャノン・ナノテクノロジーズ・インコーポレーテッド | サブ20nmの図案の均一なインプリントパターン転写方法 |
| KR102279239B1 (ko) | 2014-07-25 | 2021-07-19 | 삼성전자주식회사 | 임프린트 공정을 이용한 역상 패턴 전사방법 |
| US10580659B2 (en) | 2017-09-14 | 2020-03-03 | Canon Kabushiki Kaisha | Planarization process and apparatus |
| US10304744B1 (en) | 2018-05-15 | 2019-05-28 | International Business Machines Corporation | Inverse tone direct print EUV lithography enabled by selective material deposition |
| US11398377B2 (en) | 2020-01-14 | 2022-07-26 | International Business Machines Corporation | Bilayer hardmask for direct print lithography |
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-
2005
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- 2005-05-19 WO PCT/US2005/017756 patent/WO2005114719A2/en not_active Ceased
- 2005-05-19 CN CN200580016113.XA patent/CN101356303B/zh not_active Expired - Lifetime
- 2005-05-19 JP JP2007527480A patent/JP5059608B2/ja not_active Expired - Lifetime
- 2005-05-19 KR KR1020067024158A patent/KR101139302B1/ko not_active Expired - Fee Related
- 2005-05-20 TW TW094116565A patent/TWI289326B/zh not_active IP Right Cessation
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- 2011-12-02 JP JP2011264596A patent/JP5563544B2/ja not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2005114719A2 (en) | 2005-12-01 |
| CN101356303B (zh) | 2012-04-04 |
| TW200603261A (en) | 2006-01-16 |
| JP5059608B2 (ja) | 2012-10-24 |
| JP2008517448A (ja) | 2008-05-22 |
| TWI289326B (en) | 2007-11-01 |
| JP2012054612A (ja) | 2012-03-15 |
| JP5563544B2 (ja) | 2014-07-30 |
| KR20070013305A (ko) | 2007-01-30 |
| CN101356303A (zh) | 2009-01-28 |
| US20050260848A1 (en) | 2005-11-24 |
| WO2005114719A3 (en) | 2008-10-09 |
| EP1761949A2 (en) | 2007-03-14 |
| US7186656B2 (en) | 2007-03-06 |
| EP1761949A4 (en) | 2011-04-20 |
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