KR101037246B1 - 멀티 칩 리드 프레임 패키지 - Google Patents

멀티 칩 리드 프레임 패키지 Download PDF

Info

Publication number
KR101037246B1
KR101037246B1 KR1020077007844A KR20077007844A KR101037246B1 KR 101037246 B1 KR101037246 B1 KR 101037246B1 KR 1020077007844 A KR1020077007844 A KR 1020077007844A KR 20077007844 A KR20077007844 A KR 20077007844A KR 101037246 B1 KR101037246 B1 KR 101037246B1
Authority
KR
South Korea
Prior art keywords
die
lead frame
paddle
cavity
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1020077007844A
Other languages
English (en)
Korean (ko)
Other versions
KR20070095865A (ko
Inventor
종우 하
태복 정
Original Assignee
스태츠 칩팩, 엘티디.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 스태츠 칩팩, 엘티디. filed Critical 스태츠 칩팩, 엘티디.
Publication of KR20070095865A publication Critical patent/KR20070095865A/ko
Application granted granted Critical
Publication of KR101037246B1 publication Critical patent/KR101037246B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
KR1020077007844A 2004-10-18 2005-10-17 멀티 칩 리드 프레임 패키지 Expired - Lifetime KR101037246B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61984704P 2004-10-18 2004-10-18
US60/619,847 2004-10-18

Publications (2)

Publication Number Publication Date
KR20070095865A KR20070095865A (ko) 2007-10-01
KR101037246B1 true KR101037246B1 (ko) 2011-05-26

Family

ID=36203633

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077007844A Expired - Lifetime KR101037246B1 (ko) 2004-10-18 2005-10-17 멀티 칩 리드 프레임 패키지

Country Status (5)

Country Link
US (2) US7208821B2 (enExample)
JP (1) JP5011115B2 (enExample)
KR (1) KR101037246B1 (enExample)
TW (1) TWI404184B (enExample)
WO (1) WO2006044804A2 (enExample)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745918B1 (en) 2004-11-24 2010-06-29 Amkor Technology, Inc. Package in package (PiP)
US20070108635A1 (en) * 2005-04-28 2007-05-17 Stats Chippac Ltd. Integrated circuit package system
US20070130759A1 (en) * 2005-06-15 2007-06-14 Gem Services, Inc. Semiconductor device package leadframe formed from multiple metal layers
US8803299B2 (en) * 2006-02-27 2014-08-12 Stats Chippac Ltd. Stacked integrated circuit package system
US7961470B2 (en) * 2006-07-19 2011-06-14 Infineon Technologies Ag Power amplifier
US20080054429A1 (en) * 2006-08-25 2008-03-06 Bolken Todd O Spacers for separating components of semiconductor device assemblies, semiconductor device assemblies and systems including spacers and methods of making spacers
KR100809701B1 (ko) * 2006-09-05 2008-03-06 삼성전자주식회사 칩간 열전달 차단 스페이서를 포함하는 멀티칩 패키지
US7271485B1 (en) 2006-09-11 2007-09-18 Agere Systems Inc. Systems and methods for distributing I/O in a semiconductor device
US20080079149A1 (en) * 2006-09-28 2008-04-03 Harry Hedler Circuit board arrangement and method for producing a circuit board arrangement
JP4860442B2 (ja) * 2006-11-20 2012-01-25 ローム株式会社 半導体装置
US20080157307A1 (en) * 2006-12-28 2008-07-03 Semiconductor Manufacturing International (Shanghai) Corporation Lead frame
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
TW200921885A (en) * 2007-11-06 2009-05-16 Powertech Technology Inc Package on package structure
US8643157B2 (en) * 2007-06-21 2014-02-04 Stats Chippac Ltd. Integrated circuit package system having perimeter paddle
US7919848B2 (en) * 2007-08-03 2011-04-05 Stats Chippac Ltd. Integrated circuit package system with multiple devices
CN100530636C (zh) * 2007-11-09 2009-08-19 中国科学院上海微系统与信息技术研究所 三维多芯片封装模块和制作方法
US7692311B2 (en) * 2007-11-21 2010-04-06 Powertech Technology Inc. POP (package-on-package) device encapsulating soldered joints between external leads
US8618653B2 (en) * 2008-01-30 2013-12-31 Stats Chippac Ltd. Integrated circuit package system with wafer scale heat slug
US8664038B2 (en) * 2008-12-04 2014-03-04 Stats Chippac Ltd. Integrated circuit packaging system with stacked paddle and method of manufacture thereof
US8034662B2 (en) * 2009-03-18 2011-10-11 Advanced Micro Devices, Inc. Thermal interface material with support structure
US20100252918A1 (en) * 2009-04-06 2010-10-07 Jiang Hunt H Multi-die package with improved heat dissipation
US7994615B2 (en) * 2009-08-28 2011-08-09 International Rectifier Corporation Direct contact leadless package for high current devices
US8093695B2 (en) 2009-09-04 2012-01-10 International Rectifier Corporation Direct contact leadless flip chip package for high current devices
KR101119473B1 (ko) * 2009-10-07 2012-03-16 이성규 반도체 패키지 및 그 제조방법
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
US8207015B2 (en) * 2010-04-30 2012-06-26 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US20120193772A1 (en) * 2011-01-28 2012-08-02 Hunt Hang Jiang Stacked die packages with flip-chip and wire bonding dies
US9524957B2 (en) * 2011-08-17 2016-12-20 Intersil Americas LLC Back-to-back stacked dies
KR101354894B1 (ko) * 2011-10-27 2014-01-23 삼성전기주식회사 반도체 패키지, 그 제조방법 및 이를 포함하는 반도체 패키지 모듈
JP2013149779A (ja) * 2012-01-19 2013-08-01 Semiconductor Components Industries Llc 半導体装置
JP5620437B2 (ja) * 2012-05-18 2014-11-05 ラピスセミコンダクタ株式会社 半導体装置
US8759956B2 (en) * 2012-07-05 2014-06-24 Infineon Technologies Ag Chip package and method of manufacturing the same
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
KR101538543B1 (ko) * 2013-08-13 2015-07-22 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
TWI550823B (zh) * 2014-04-10 2016-09-21 南茂科技股份有限公司 晶片封裝結構
JP2017147272A (ja) 2016-02-15 2017-08-24 ローム株式会社 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体
US11211305B2 (en) 2016-04-01 2021-12-28 Texas Instruments Incorporated Apparatus and method to support thermal management of semiconductor-based components
US10861796B2 (en) 2016-05-10 2020-12-08 Texas Instruments Incorporated Floating die package
EP3261115A1 (en) 2016-06-23 2017-12-27 Nxp B.V. Chip scale semiconductor package and method of manufacturing the same
US10179730B2 (en) 2016-12-08 2019-01-15 Texas Instruments Incorporated Electronic sensors with sensor die in package structure cavity
US10411150B2 (en) 2016-12-30 2019-09-10 Texas Instruments Incorporated Optical isolation systems and circuits and photon detectors with extended lateral P-N junctions
US9929110B1 (en) 2016-12-30 2018-03-27 Texas Instruments Incorporated Integrated circuit wave device and method
US10074639B2 (en) 2016-12-30 2018-09-11 Texas Instruments Incorporated Isolator integrated circuits with package structure cavity and fabrication methods
US10121847B2 (en) 2017-03-17 2018-11-06 Texas Instruments Incorporated Galvanic isolation device
US11430722B2 (en) * 2017-04-12 2022-08-30 Texas Instruments Incorporated Integration of a passive component in a cavity of an integrated circuit package
US10600769B2 (en) * 2017-09-01 2020-03-24 Airoha Technology Group Electronic component
US10418343B2 (en) * 2017-12-05 2019-09-17 Infineon Technologies Ag Package-in-package structure for semiconductor devices and methods of manufacture
US10593612B2 (en) 2018-03-19 2020-03-17 Stmicroelectronics S.R.L. SMDs integration on QFN by 3D stacked solution
US20190287881A1 (en) 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
US11177301B2 (en) * 2018-11-19 2021-11-16 UTAC Headquarters Pte. Ltd. Reliable semiconductor packages
US11817423B2 (en) 2019-07-29 2023-11-14 Intel Corporation Double-sided substrate with cavities for direct die-to-die interconnect
TWI781863B (zh) * 2021-12-30 2022-10-21 宏齊科技股份有限公司 平面式多晶片裝置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150765A (ja) 1998-10-21 2000-05-30 Amkor Technology Inc 半導体集積回路プラスチックパッケ―ジ、およびそのパッケ―ジの製造のための超小型リ―ドフレ―ムおよび製造方法
JP2002208664A (ja) 2001-01-12 2002-07-26 Rohm Co Ltd リードフレームの製造方法および半導体装置
JP2002231871A (ja) 2001-02-06 2002-08-16 Toppan Printing Co Ltd リードフレームの製造方法及びリードフレーム

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3531886A1 (de) * 1985-09-06 1987-03-19 Stankiewicz Alois Dr Gmbh Hohlkammern
JP2902918B2 (ja) * 1993-11-25 1999-06-07 三洋電機株式会社 表面実装型半導体装置
JP3638750B2 (ja) * 1997-03-25 2005-04-13 株式会社ルネサステクノロジ 半導体装置
JP3670853B2 (ja) * 1998-07-30 2005-07-13 三洋電機株式会社 半導体装置
US6261865B1 (en) * 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
JP3730469B2 (ja) * 2000-01-21 2006-01-05 新電元工業株式会社 樹脂封止型半導体装置及びその製造方法
KR100559664B1 (ko) * 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP3442721B2 (ja) * 2000-05-24 2003-09-02 沖電気工業株式会社 半導体装置
US6608375B2 (en) * 2001-04-06 2003-08-19 Oki Electric Industry Co., Ltd. Semiconductor apparatus with decoupling capacitor
DE10142117A1 (de) * 2001-08-30 2003-03-27 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung
TWI268581B (en) * 2002-01-25 2006-12-11 Advanced Semiconductor Eng Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material
KR100460062B1 (ko) * 2002-04-23 2004-12-04 주식회사 하이닉스반도체 멀티 칩 패키지 및 그 제조 방법
JP3550391B2 (ja) * 2002-05-15 2004-08-04 沖電気工業株式会社 半導体装置及びその製造方法
TW548810B (en) * 2002-05-31 2003-08-21 Gigno Technology Co Ltd Multi-chip package
US7005325B2 (en) * 2004-02-05 2006-02-28 St Assembly Test Services Ltd. Semiconductor package with passive device integration

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150765A (ja) 1998-10-21 2000-05-30 Amkor Technology Inc 半導体集積回路プラスチックパッケ―ジ、およびそのパッケ―ジの製造のための超小型リ―ドフレ―ムおよび製造方法
JP2002208664A (ja) 2001-01-12 2002-07-26 Rohm Co Ltd リードフレームの製造方法および半導体装置
JP2002231871A (ja) 2001-02-06 2002-08-16 Toppan Printing Co Ltd リードフレームの製造方法及びリードフレーム

Also Published As

Publication number Publication date
KR20070095865A (ko) 2007-10-01
US20060081967A1 (en) 2006-04-20
JP2008517482A (ja) 2008-05-22
US7208821B2 (en) 2007-04-24
WO2006044804A3 (en) 2007-04-19
WO2006044804A2 (en) 2006-04-27
US20070152308A1 (en) 2007-07-05
TWI404184B (zh) 2013-08-01
JP5011115B2 (ja) 2012-08-29
TW200629516A (en) 2006-08-16
US7436048B2 (en) 2008-10-14

Similar Documents

Publication Publication Date Title
KR101037246B1 (ko) 멀티 칩 리드 프레임 패키지
US6936929B1 (en) Multichip packages with exposed dice
US8373277B2 (en) Stacked die in die BGA package
JP3420153B2 (ja) 半導体装置及びその製造方法
US6909168B2 (en) Resin encapsulation semiconductor device utilizing grooved leads and die pad
US6723585B1 (en) Leadless package
JP3420057B2 (ja) 樹脂封止型半導体装置
KR100716871B1 (ko) 반도체패키지용 캐리어프레임 및 이를 이용한반도체패키지와 그 제조 방법
KR101166575B1 (ko) 적층형 패키지들 간 도선연결에 의한 상호연결을 이용한반도체 멀티-패키지 모듈 및 그 제작 방법
JP5227501B2 (ja) スタックダイパッケージ及びそれを製造する方法
US20020039811A1 (en) A method of manufacturing a semiconductor device
TWI430425B (zh) 採用凸塊技術之積體電路封裝件系統
US7161232B1 (en) Apparatus and method for miniature semiconductor packages
CN212182312U (zh) 半导体封装件
US7023096B2 (en) Multi-chip package having spacer that is inserted between chips and manufacturing method thereof
US7687920B2 (en) Integrated circuit package-on-package system with central bond wires
US7759783B2 (en) Integrated circuit package system employing thin profile techniques
KR100256304B1 (ko) 적층형 패키지
KR100747996B1 (ko) 반도체 패키지
KR20030018207A (ko) 반도체 칩 실장 밀도를 향상시킨 멀티 칩 패키지 및씨오비 패키지
KR20060017165A (ko) 듀얼 게이지 리드프레임
KR20060068971A (ko) 적층 패키지
KR100370480B1 (ko) 반도체 패키지용 리드 프레임

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20070406

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
A302 Request for accelerated examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20101015

Comment text: Request for Examination of Application

PA0302 Request for accelerated examination

Patent event date: 20101015

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20101203

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20110228

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20110519

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20110519

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
FPAY Annual fee payment

Payment date: 20140512

Year of fee payment: 4

PR1001 Payment of annual fee

Payment date: 20140512

Start annual number: 4

End annual number: 4

FPAY Annual fee payment

Payment date: 20150508

Year of fee payment: 5

PR1001 Payment of annual fee

Payment date: 20150508

Start annual number: 5

End annual number: 5

FPAY Annual fee payment

Payment date: 20160510

Year of fee payment: 6

PR1001 Payment of annual fee

Payment date: 20160510

Start annual number: 6

End annual number: 6

FPAY Annual fee payment

Payment date: 20170508

Year of fee payment: 7

PR1001 Payment of annual fee

Payment date: 20170508

Start annual number: 7

End annual number: 7

FPAY Annual fee payment

Payment date: 20180509

Year of fee payment: 8

PR1001 Payment of annual fee

Payment date: 20180509

Start annual number: 8

End annual number: 8

FPAY Annual fee payment

Payment date: 20190516

Year of fee payment: 9

PR1001 Payment of annual fee

Payment date: 20190516

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20200513

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20210512

Start annual number: 11

End annual number: 11