KR100649410B1 - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR100649410B1
KR100649410B1 KR1020000077907A KR20000077907A KR100649410B1 KR 100649410 B1 KR100649410 B1 KR 100649410B1 KR 1020000077907 A KR1020000077907 A KR 1020000077907A KR 20000077907 A KR20000077907 A KR 20000077907A KR 100649410 B1 KR100649410 B1 KR 100649410B1
Authority
KR
South Korea
Prior art keywords
insulating film
etching
interlayer insulating
film
etch stopper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1020000077907A
Other languages
English (en)
Korean (ko)
Other versions
KR20020009381A (ko
Inventor
와따나베겐이찌
고마다다이수께
심푸꾸후미히꼬
Original Assignee
후지쯔 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쯔 가부시끼가이샤 filed Critical 후지쯔 가부시끼가이샤
Publication of KR20020009381A publication Critical patent/KR20020009381A/ko
Application granted granted Critical
Publication of KR100649410B1 publication Critical patent/KR100649410B1/ko
Assigned to 후지쯔 세미컨덕터 가부시키가이샤 reassignment 후지쯔 세미컨덕터 가부시키가이샤 권리의 전부이전등록 Assignors: 후지쯔 가부시끼가이샤
Assigned to 가부시키가이샤 소시오넥스트 reassignment 가부시키가이샤 소시오넥스트 권리의 전부이전등록 Assignors: 후지쯔 세미컨덕터 가부시키가이샤
Assigned to 트리니티 세미컨덕터 리서치 고도가이샤 reassignment 트리니티 세미컨덕터 리서치 고도가이샤 권리의 전부이전등록 Assignors: 가부시키가이샤 소시오넥스트
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020000077907A 2000-07-21 2000-12-18 반도체 장치 및 그 제조 방법 Expired - Lifetime KR100649410B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-221202 2000-07-21
JP2000221202A JP4858895B2 (ja) 2000-07-21 2000-07-21 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR20020009381A KR20020009381A (ko) 2002-02-01
KR100649410B1 true KR100649410B1 (ko) 2006-11-24

Family

ID=18715655

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000077907A Expired - Lifetime KR100649410B1 (ko) 2000-07-21 2000-12-18 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (2) US6787907B2 (https=)
JP (1) JP4858895B2 (https=)
KR (1) KR100649410B1 (https=)
TW (1) TW471045B (https=)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294799B1 (en) * 1995-11-27 2001-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
JP3920590B2 (ja) * 2000-06-19 2007-05-30 株式会社東芝 半導体装置の製造方法
US7172960B2 (en) * 2000-12-27 2007-02-06 Intel Corporation Multi-layer film stack for extinction of substrate reflections during patterning
JP4948715B2 (ja) * 2001-06-29 2012-06-06 富士通セミコンダクター株式会社 半導体ウエハ装置およびその製造方法
US7183195B2 (en) 2002-02-22 2007-02-27 Samsung Electronics, Co., Ltd. Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler
JP3762732B2 (ja) * 2002-09-27 2006-04-05 三洋電機株式会社 半導体装置の製造方法
JP3909283B2 (ja) * 2002-10-31 2007-04-25 富士通株式会社 半導体装置の製造方法
KR100960921B1 (ko) * 2002-11-20 2010-06-04 매그나칩 반도체 유한회사 반도체 소자의 금속 배선 형성 방법
JP3977246B2 (ja) 2002-12-27 2007-09-19 富士通株式会社 半導体装置及びその製造方法
US7675174B2 (en) * 2003-05-13 2010-03-09 Stmicroelectronics, Inc. Method and structure of a thick metal layer using multiple deposition chambers
JP4571785B2 (ja) * 2003-05-30 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100598294B1 (ko) 2003-12-31 2006-07-07 동부일렉트로닉스 주식회사 듀얼 다마신을 이용한 구리 배선 형성 방법
JP4211674B2 (ja) * 2004-05-12 2009-01-21 セイコーエプソン株式会社 半導体装置及びその製造方法、電気光学装置及びその製造方法、並びに電子機器
US7053004B2 (en) * 2004-05-14 2006-05-30 Sharp Kabushiki Kaisha Decreasing the residue of a silicon dioxide layer after trench etching
US7572727B1 (en) * 2004-09-02 2009-08-11 Spansion Llc Semiconductor formation method that utilizes multiple etch stop layers
DE102005004409B4 (de) * 2005-01-31 2011-01-20 Advanced Micro Devices, Inc., Sunnyvale Technik zur Erhöhung der Prozessflexibilität während der Herstellung von Kontaktdurchführungen und Gräben in Zwischenschichtdielektrika mit kleinem ε
US20060244151A1 (en) * 2005-05-02 2006-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Oblique recess for interconnecting conductors in a semiconductor device
JP2006351862A (ja) * 2005-06-16 2006-12-28 Toshiba Corp 半導体装置の製造方法
US7531448B2 (en) * 2005-06-22 2009-05-12 United Microelectronics Corp. Manufacturing method of dual damascene structure
JP5096669B2 (ja) * 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US20070057305A1 (en) 2005-09-13 2007-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitor integrated into the damascene structure and method of making thereof
US7244660B2 (en) * 2005-10-31 2007-07-17 Spansion Llc Method for manufacturing a semiconductor component
JP4533304B2 (ja) * 2005-11-29 2010-09-01 富士通セミコンダクター株式会社 半導体装置の製造方法
US8264086B2 (en) 2005-12-05 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure with improved reliability
CN101667555B (zh) * 2005-12-07 2012-06-27 佳能株式会社 使用双镶嵌工艺制造半导体器件的方法以及制造具有连通孔的制品的方法
US7964470B2 (en) 2006-03-01 2011-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible processing method for metal-insulator-metal capacitor formation
JP4728153B2 (ja) * 2006-03-20 2011-07-20 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2008047582A (ja) * 2006-08-11 2008-02-28 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP5103006B2 (ja) * 2006-11-16 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4901453B2 (ja) * 2006-12-20 2012-03-21 東芝ディスクリートテクノロジー株式会社 半導体発光素子
KR100922989B1 (ko) * 2007-04-25 2009-10-22 주식회사 하이닉스반도체 플래시 메모리 소자 및 그것의 제조방법
US7884019B2 (en) * 2007-06-07 2011-02-08 Texas Instruments Incorporated Poison-free and low ULK damage integration scheme for damascene interconnects
US7456030B1 (en) * 2007-10-11 2008-11-25 National Semiconductor Corporation Electroforming technique for the formation of high frequency performance ferromagnetic films
JP2010050311A (ja) 2008-08-22 2010-03-04 Elpida Memory Inc 半導体装置及びその製造方法
JP2011165924A (ja) * 2010-02-10 2011-08-25 Mitsubishi Electric Corp 半導体装置
US8421239B2 (en) * 2010-03-16 2013-04-16 International Business Machines Corporation Crenulated wiring structure and method for integrated circuit interconnects
JP2012015197A (ja) * 2010-06-29 2012-01-19 Tokyo Electron Ltd 半導体装置の配線形成方法、半導体装置の製造方法および半導体装置の配線形成システム
US9860985B1 (en) 2012-12-17 2018-01-02 Lockheed Martin Corporation System and method for improving isolation in high-density laminated printed circuit boards
US9142452B2 (en) 2013-07-22 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask removal scheme
US9536826B1 (en) * 2015-06-15 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finFET) device structure with interconnect structure
US10332790B2 (en) 2015-06-15 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with interconnect structure
US9570397B1 (en) * 2015-12-10 2017-02-14 International Business Machines Corporation Local interconnect structure including non-eroded contact via trenches
KR102547096B1 (ko) * 2015-12-22 2023-06-26 에스케이하이닉스 주식회사 듀얼다마신구조를 형성하는 방법
US9859156B2 (en) * 2015-12-30 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure with sidewall dielectric protection layer
CN108666274B (zh) * 2017-03-31 2020-10-27 联华电子股份有限公司 半导体存储装置的形成方法
KR102460076B1 (ko) 2017-08-01 2022-10-28 삼성전자주식회사 반도체 장치
KR102356754B1 (ko) * 2017-08-02 2022-01-27 삼성전자주식회사 반도체 장치
TWI642333B (zh) 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法
TWI642334B (zh) 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法
DE102018123499A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Prozesssteuerung für Package-Herstellung
US10811309B2 (en) * 2018-12-04 2020-10-20 Nanya Technology Corporation Semiconductor structure and fabrication thereof
CN110379762B (zh) * 2019-06-10 2020-05-19 长江存储科技有限责任公司 一种半导体结构及其制作方法
US11018256B2 (en) * 2019-08-23 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Selective internal gate structure for ferroelectric semiconductor devices
US11652049B2 (en) 2021-03-10 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming thereof
KR20220135762A (ko) * 2021-03-31 2022-10-07 삼성전기주식회사 인쇄회로기판

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10112503A (ja) * 1996-10-03 1998-04-28 Sony Corp 半導体装置の製造方法
KR20000042812A (ko) * 1998-12-26 2000-07-15 윤종용 반도체 장치의 제조 방법
KR20010046918A (ko) * 1999-11-16 2001-06-15 박종섭 이중 상감 금속 배선의 형성 방법
JP2001168188A (ja) * 1999-12-06 2001-06-22 Sony Corp 半導体装置の製造方法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874201A (en) * 1995-06-05 1999-02-23 International Business Machines Corporation Dual damascene process having tapered vias
JPH1064995A (ja) * 1996-08-23 1998-03-06 Sony Corp 半導体装置の製造方法
JP3713869B2 (ja) * 1997-02-17 2005-11-09 ソニー株式会社 半導体装置の製造方法
GB2325083B (en) * 1997-05-09 1999-04-14 United Microelectronics Corp A dual damascene process
US5801094A (en) * 1997-02-28 1998-09-01 United Microelectronics Corporation Dual damascene process
JPH10242271A (ja) * 1997-02-28 1998-09-11 Sony Corp 半導体装置及びその製造方法
JP3183238B2 (ja) * 1997-11-27 2001-07-09 日本電気株式会社 半導体装置の製造方法
JPH11233630A (ja) * 1998-02-18 1999-08-27 Sony Corp 半導体装置の製造方法およびこれを用いた半導体装置
US6042999A (en) * 1998-05-07 2000-03-28 Taiwan Semiconductor Manufacturing Company Robust dual damascene process
TW383463B (en) * 1998-06-01 2000-03-01 United Microelectronics Corp Manufacturing method for dual damascene structure
US6326296B1 (en) * 1998-07-01 2001-12-04 Taiwan Semiconductor Manufacturing Company Method of forming dual damascene structure with improved contact/via edge integrity
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
JP3501280B2 (ja) * 1998-08-31 2004-03-02 富士通株式会社 半導体装置の製造方法
JP3189970B2 (ja) * 1998-09-07 2001-07-16 日本電気株式会社 半導体装置の製造方法
US6284149B1 (en) * 1998-09-18 2001-09-04 Applied Materials, Inc. High-density plasma etching of carbon-based low-k materials in a integrated circuit
JP3734390B2 (ja) * 1998-10-21 2006-01-11 東京応化工業株式会社 埋込材およびこの埋込材を用いた配線形成方法
US6184142B1 (en) * 1999-04-26 2001-02-06 United Microelectronics Corp. Process for low k organic dielectric film etch
US6461955B1 (en) * 1999-04-29 2002-10-08 Texas Instruments Incorporated Yield improvement of dual damascene fabrication through oxide filling
US6096595A (en) * 1999-05-12 2000-08-01 Taiwan Semiconductor Manufacturing Company Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
KR20010019643A (ko) * 1999-08-28 2001-03-15 윤종용 저유전율 절연막을 갖는 다층 금속배선의 형성방법
US6429119B1 (en) * 1999-09-27 2002-08-06 Taiwan Semiconductor Manufacturing Company Dual damascene process to reduce etch barrier thickness
JP2001102447A (ja) * 1999-09-30 2001-04-13 Mitsubishi Electric Corp コンタクト構造の製造方法
US6319814B1 (en) * 1999-10-12 2001-11-20 United Microelectronics Corp. Method of fabricating dual damascene
US6211061B1 (en) * 1999-10-29 2001-04-03 Taiwan Semiconductor Manufactuirng Company Dual damascene process for carbon-based low-K materials
US6319821B1 (en) * 2000-04-24 2001-11-20 Taiwan Semiconductor Manufacturing Company Dual damascene approach for small geometry dimension
JP2001332618A (ja) * 2000-05-23 2001-11-30 Nec Corp 半導体装置
US6316351B1 (en) * 2000-05-31 2001-11-13 Taiwan Semiconductor Manufacturing Company Inter-metal dielectric film composition for dual damascene process
US6342448B1 (en) * 2000-05-31 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process
US6319809B1 (en) * 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
US6365508B1 (en) * 2000-07-18 2002-04-02 Chartered Semiconductor Manufacturing Ltd. Process without post-etch cleaning-converting polymer and by-products into an inert layer
US6475810B1 (en) * 2000-08-10 2002-11-05 Chartered Semiconductor Manufacturing Ltd. Method of manufacturing embedded organic stop layer for dual damascene patterning
US6455411B1 (en) * 2000-09-11 2002-09-24 Texas Instruments Incorporated Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics
US6797633B2 (en) * 2000-11-09 2004-09-28 Texas Instruments Incorporated In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
TW468241B (en) * 2000-11-14 2001-12-11 United Microelectronics Corp Method to improve adhesion of dielectric material of semiconductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10112503A (ja) * 1996-10-03 1998-04-28 Sony Corp 半導体装置の製造方法
KR20000042812A (ko) * 1998-12-26 2000-07-15 윤종용 반도체 장치의 제조 방법
KR20010046918A (ko) * 1999-11-16 2001-06-15 박종섭 이중 상감 금속 배선의 형성 방법
JP2001168188A (ja) * 1999-12-06 2001-06-22 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US20050001323A1 (en) 2005-01-06
US6787907B2 (en) 2004-09-07
JP2002043417A (ja) 2002-02-08
TW471045B (en) 2002-01-01
JP4858895B2 (ja) 2012-01-18
US20020008323A1 (en) 2002-01-24
KR20020009381A (ko) 2002-02-01
US7119009B2 (en) 2006-10-10

Similar Documents

Publication Publication Date Title
KR100649410B1 (ko) 반도체 장치 및 그 제조 방법
JP4118029B2 (ja) 半導体集積回路装置とその製造方法
US7538023B2 (en) Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area
JP2002313910A (ja) 半導体装置とその製造方法
US6054380A (en) Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure
US6372635B1 (en) Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer
US6372631B1 (en) Method of making a via filled dual damascene structure without middle stop layer
JP4050876B2 (ja) 半導体集積回路装置とその製造方法
EP1610376B1 (en) Semiconductor device
US6383919B1 (en) Method of making a dual damascene structure without middle stop layer
JP5104924B2 (ja) 半導体装置
US6429116B1 (en) Method of fabricating a slot dual damascene structure without middle stop layer
US6465340B1 (en) Via filled dual damascene structure with middle stop layer and method for making the same
JP4211910B2 (ja) 半導体装置の製造方法
US6365505B1 (en) Method of making a slot via filled dual damascene structure with middle stop layer
KR100613283B1 (ko) 반도체 소자의 배선 형성방법
US6444573B1 (en) Method of making a slot via filled dual damascene structure with a middle stop layer
JP2005197694A (ja) 半導体集積回路の配線製造方法
KR100784106B1 (ko) 반도체 소자의 금속 배선 형성 방법
KR100703097B1 (ko) 반도체 장치
KR20240068324A (ko) 고 내압 캐패시터를 가지는 반도체 소자 제조 방법
KR20000044863A (ko) 반도체 소자의 층간 절연막 평탄화 방법
WO2002063676A2 (en) A slot via filled dual damascene structure without middle stop layer and method for making the same
KR20000013330A (ko) 반도체 소자 및 반도체 소자의 배선형성방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

FPAY Annual fee payment

Payment date: 20091110

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

FPAY Annual fee payment

Payment date: 20101116

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20111019

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20121023

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20131022

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20141021

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

FPAY Annual fee payment

Payment date: 20151016

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20161019

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

FPAY Annual fee payment

Payment date: 20171018

Year of fee payment: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

FPAY Annual fee payment

Payment date: 20181018

Year of fee payment: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

FPAY Annual fee payment

Payment date: 20191016

Year of fee payment: 14

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 14

FPAY Annual fee payment

Payment date: 20201015

Year of fee payment: 15

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 15

EXPY Expiration of term
PC1801 Expiration of term

St.27 status event code: N-4-6-H10-H14-oth-PC1801

Not in force date: 20201219

Ip right cessation event data comment text: Termination Category : EXPIRATION_OF_DURATION

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000