JPH1126757A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JPH1126757A
JPH1126757A JP9174199A JP17419997A JPH1126757A JP H1126757 A JPH1126757 A JP H1126757A JP 9174199 A JP9174199 A JP 9174199A JP 17419997 A JP17419997 A JP 17419997A JP H1126757 A JPH1126757 A JP H1126757A
Authority
JP
Japan
Prior art keywords
film
gate
gate electrode
insulating film
contact plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9174199A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1126757A5 (enExample
Inventor
Katsuhiko Hieda
克彦 稗田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP9174199A priority Critical patent/JPH1126757A/ja
Priority to US09/105,021 priority patent/US6072221A/en
Priority to KR1019980025483A priority patent/KR100307124B1/ko
Publication of JPH1126757A publication Critical patent/JPH1126757A/ja
Publication of JPH1126757A5 publication Critical patent/JPH1126757A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP9174199A 1997-06-30 1997-06-30 半導体装置及びその製造方法 Pending JPH1126757A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP9174199A JPH1126757A (ja) 1997-06-30 1997-06-30 半導体装置及びその製造方法
US09/105,021 US6072221A (en) 1997-06-30 1998-06-26 Semiconductor device having self-aligned contact plug and metallized gate electrode
KR1019980025483A KR100307124B1 (ko) 1997-06-30 1998-06-30 반도체장치및그제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9174199A JPH1126757A (ja) 1997-06-30 1997-06-30 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPH1126757A true JPH1126757A (ja) 1999-01-29
JPH1126757A5 JPH1126757A5 (enExample) 2005-04-28

Family

ID=15974466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9174199A Pending JPH1126757A (ja) 1997-06-30 1997-06-30 半導体装置及びその製造方法

Country Status (3)

Country Link
US (1) US6072221A (enExample)
JP (1) JPH1126757A (enExample)
KR (1) KR100307124B1 (enExample)

Cited By (22)

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Publication number Priority date Publication date Assignee Title
WO1999023694A1 (fr) * 1997-11-05 1999-05-14 Tokyo Electron Limited Structure de cablage de composant a semi-conducteur, electrode, et procede de fabrication de celles-ci
KR20010003682A (ko) * 1999-06-24 2001-01-15 김영환 자기정렬식 게이트전극 형성방법
KR100345069B1 (ko) * 1999-06-30 2002-07-19 주식회사 하이닉스반도체 반도체 소자의 폴리실리콘 플러그 형성방법
JP2003068731A (ja) * 2001-08-29 2003-03-07 Tokyo Electron Ltd 絶縁膜の形成方法および形成システム
US6548871B1 (en) 1999-10-27 2003-04-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer
US6607979B1 (en) 1999-09-30 2003-08-19 Nec Corporation Semiconductor device and method of producing the same
KR100400030B1 (ko) * 2000-06-05 2003-09-29 삼성전자주식회사 금속막의 화학 및 기계적 연마용 슬러리 및 그 제조방법과상기 슬러리를 이용한 반도체 소자의 금속 배선 형성 방법
JP2003536259A (ja) * 2000-06-09 2003-12-02 コミツサリア タ レネルジー アトミーク ダマシーンアーキテクチャーにおいて自己位置合わせされたソース・ドレイン・ゲートを有してなる電子素子の形成方法
KR100433093B1 (ko) * 1999-12-31 2004-05-27 주식회사 하이닉스반도체 반도체소자의 제조방법
US6759720B2 (en) 2000-07-21 2004-07-06 Renesas Technology Corp. Semiconductor device with transfer gate having gate insulating film and gate electrode layer
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6946376B2 (en) 2000-02-08 2005-09-20 International Business Machines Corporation Symmetric device with contacts self aligned to gate
KR100643571B1 (ko) * 2000-12-30 2006-11-10 주식회사 하이닉스반도체 금속 대머신 게이트 형성방법
JP2006332584A (ja) * 2005-05-25 2006-12-07 Hynix Semiconductor Inc 半導体素子の製造方法
JP2007110077A (ja) * 2005-10-12 2007-04-26 Hynix Semiconductor Inc 半導体素子のコンタクトホール形成方法
WO2007066937A1 (en) * 2005-12-06 2007-06-14 Electronics And Telecommunications Research Institute Method of manufacturing semiconductor device
JP2009099738A (ja) * 2007-10-16 2009-05-07 Toshiba Corp 半導体装置、半導体装置の製造方法及び半導体記憶装置の製造方法
JP2009524215A (ja) * 2006-01-13 2009-06-25 マイクロン テクノロジー， インク． 半導体デバイスにおいて付加的金属ルーティングを形成するためのシステムおよび方法
US7645653B2 (en) 2006-08-25 2010-01-12 Elpida Memory, Inc. Method for manufacturing a semiconductor device having a polymetal gate electrode structure
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
JP2011520297A (ja) * 2008-06-30 2011-07-14 インテル・コーポレーション 積層トレンチコンタクトを形成する方法および当該方法によって形成される構造
JP2013089712A (ja) * 2011-10-17 2013-05-13 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法

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JP3175700B2 (ja) * 1998-08-24 2001-06-11 日本電気株式会社 メタルゲート電界効果トランジスタの製造方法
US6096644A (en) * 1998-09-08 2000-08-01 Advanced Micro Devices, Inc. Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides
US6432803B1 (en) * 1998-12-14 2002-08-13 Matsushita Electric Industrial Co., Inc. Semiconductor device and method of fabricating the same
KR100338104B1 (ko) * 1999-06-30 2002-05-24 박종섭 반도체 소자의 제조 방법
KR100356136B1 (ko) 1999-12-23 2002-10-19 동부전자 주식회사 반도체 장치 제조 방법
KR100314473B1 (ko) 1999-12-23 2001-11-15 한신혁 반도체 소자 제조 방법
KR100350056B1 (ko) * 2000-03-09 2002-08-24 삼성전자 주식회사 다마신 게이트 공정에서 자기정렬콘택패드 형성 방법
KR100366617B1 (ko) * 2000-03-13 2003-01-09 삼성전자 주식회사 자기 정렬 콘택홀 제조 방법
KR100456319B1 (ko) * 2000-05-19 2004-11-10 주식회사 하이닉스반도체 폴리머와 산화막의 연마 선택비 차이를 이용한 반도체소자의 게이트 형성 방법
JP3669919B2 (ja) * 2000-12-04 2005-07-13 シャープ株式会社 半導体装置の製造方法
JP3539491B2 (ja) * 2001-02-26 2004-07-07 シャープ株式会社 半導体装置の製造方法
JP2002261277A (ja) 2001-03-06 2002-09-13 Toshiba Corp 半導体装置及びその製造方法
US6531324B2 (en) * 2001-03-28 2003-03-11 Sharp Laboratories Of America, Inc. MFOS memory transistor & method of fabricating same
KR100745951B1 (ko) * 2001-06-29 2007-08-02 주식회사 하이닉스반도체 금속 게이트 제조 방법
US6673664B2 (en) * 2001-10-16 2004-01-06 Sharp Laboratories Of America, Inc. Method of making a self-aligned ferroelectric memory transistor
JP2003224269A (ja) * 2001-10-26 2003-08-08 Hewlett Packard Co <Hp> 集積回路を製造するための装置および方法
US6740536B2 (en) * 2001-10-26 2004-05-25 Hewlett-Packard Develpment Corporation, L.P. Devices and methods for integrated circuit manufacturing
KR100444301B1 (ko) * 2001-12-29 2004-08-16 주식회사 하이닉스반도체 질화막 ｃｍｐ를 이용한 다마신 금속 게이트 형성 방법
KR100574487B1 (ko) * 2002-07-05 2006-04-27 주식회사 하이닉스반도체 반도체소자의 ｍｏｓ 트랜지스터 제조방법
US20040256671A1 (en) * 2003-06-17 2004-12-23 Kuo-Tai Huang Metal-oxide-semiconductor transistor with selective epitaxial growth film
US7521368B2 (en) * 2004-05-07 2009-04-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR100792394B1 (ko) * 2005-09-28 2008-01-09 주식회사 하이닉스반도체 반도체 소자 제조 방법
FR2915023B1 (fr) * 2007-04-13 2009-07-17 St Microelectronics Crolles 2 Realisation de contacts auto-positionnes par epitaxie
US7838373B2 (en) * 2008-07-30 2010-11-23 Intel Corporation Replacement spacers for MOSFET fringe capacitance reduction and processes of making same
US8035165B2 (en) * 2008-08-26 2011-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating a first contact structure in a gate last process
US7745275B2 (en) * 2008-09-10 2010-06-29 Arm Limited Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region
US8946828B2 (en) * 2010-02-09 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having elevated structure and method of manufacturing the same
US8373239B2 (en) 2010-06-08 2013-02-12 International Business Machines Corporation Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric
US8785322B2 (en) * 2011-01-31 2014-07-22 International Business Machines Corporation Devices and methods to optimize materials and properties for replacement metal gate structures
DE102011004323B4 (de) * 2011-02-17 2016-02-25 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement mit selbstjustierten Kontaktelementen und Verfahren zu seiner Herstellung
US8846513B2 (en) * 2011-09-23 2014-09-30 Globalfoundries Inc. Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill
CN105448683B (zh) * 2014-05-26 2019-10-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和电子装置
US10510613B2 (en) 2018-01-23 2019-12-17 Globalfoundries Inc. Contact structures
US10347541B1 (en) 2018-04-25 2019-07-09 Globalfoundries Inc. Active gate contacts and method of fabrication thereof
US10553486B1 (en) 2018-07-27 2020-02-04 Globalfoundries Inc. Field effect transistors with self-aligned metal plugs and methods
US10573753B1 (en) 2018-09-10 2020-02-25 Globalfoundries Inc. Oxide spacer in a contact over active gate finFET and method of production thereof
US10818548B1 (en) 2019-05-30 2020-10-27 International Business Machines Corporation Method and structure for cost effective enhanced self-aligned contacts

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JPH01270260A (ja) * 1988-04-21 1989-10-27 Fujitsu Ltd 半導体装置およびその製造方法
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JPH0955499A (ja) * 1995-08-11 1997-02-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5567631A (en) * 1995-11-13 1996-10-22 Taiwan Semiconductor Manufacturing Company Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology
US5804846A (en) * 1996-05-28 1998-09-08 Harris Corporation Process for forming a self-aligned raised source/drain MOS device and device therefrom
JP2964960B2 (ja) * 1996-09-27 1999-10-18 日本電気株式会社 半導体装置およびその製造方法
US5866459A (en) * 1997-02-20 1999-02-02 National Semiconductor Corporation Method of fabricating a contact structure for an MOS transistor entirely on isolation oxide
US5851883A (en) * 1997-04-23 1998-12-22 Advanced Micro Devices, Inc. High density integrated circuit process

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
WO1999023694A1 (fr) * 1997-11-05 1999-05-14 Tokyo Electron Limited Structure de cablage de composant a semi-conducteur, electrode, et procede de fabrication de celles-ci
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6838376B2 (en) 1997-11-05 2005-01-04 Tokyo Electron Limited Method of forming semiconductor wiring structures
KR20010003682A (ko) * 1999-06-24 2001-01-15 김영환 자기정렬식 게이트전극 형성방법
KR100345069B1 (ko) * 1999-06-30 2002-07-19 주식회사 하이닉스반도체 반도체 소자의 폴리실리콘 플러그 형성방법
US6607979B1 (en) 1999-09-30 2003-08-19 Nec Corporation Semiconductor device and method of producing the same
US6548871B1 (en) 1999-10-27 2003-04-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer
KR100433093B1 (ko) * 1999-12-31 2004-05-27 주식회사 하이닉스반도체 반도체소자의 제조방법
US6946376B2 (en) 2000-02-08 2005-09-20 International Business Machines Corporation Symmetric device with contacts self aligned to gate
KR100400030B1 (ko) * 2000-06-05 2003-09-29 삼성전자주식회사 금속막의 화학 및 기계적 연마용 슬러리 및 그 제조방법과상기 슬러리를 이용한 반도체 소자의 금속 배선 형성 방법
JP2003536259A (ja) * 2000-06-09 2003-12-02 コミツサリア タ レネルジー アトミーク ダマシーンアーキテクチャーにおいて自己位置合わせされたソース・ドレイン・ゲートを有してなる電子素子の形成方法
US6759720B2 (en) 2000-07-21 2004-07-06 Renesas Technology Corp. Semiconductor device with transfer gate having gate insulating film and gate electrode layer
KR100643571B1 (ko) * 2000-12-30 2006-11-10 주식회사 하이닉스반도체 금속 대머신 게이트 형성방법
JP2003068731A (ja) * 2001-08-29 2003-03-07 Tokyo Electron Ltd 絶縁膜の形成方法および形成システム
JP2006332584A (ja) * 2005-05-25 2006-12-07 Hynix Semiconductor Inc 半導体素子の製造方法
JP2007110077A (ja) * 2005-10-12 2007-04-26 Hynix Semiconductor Inc 半導体素子のコンタクトホール形成方法
WO2007066937A1 (en) * 2005-12-06 2007-06-14 Electronics And Telecommunications Research Institute Method of manufacturing semiconductor device
US7947585B2 (en) 2005-12-06 2011-05-24 Electronics And Telecommunications Research Institute Method of manufacturing semiconductor device
JP2009524215A (ja) * 2006-01-13 2009-06-25 マイクロン テクノロジー， インク． 半導体デバイスにおいて付加的金属ルーティングを形成するためのシステムおよび方法
KR101373918B1 (ko) * 2006-01-13 2014-03-12 마이크론 테크놀로지, 인크. 반도체 디바이스에서 추가의 금속 라우팅을 형성하기 위한 시스템 및 방법
US8674404B2 (en) 2006-01-13 2014-03-18 Micron Technology, Inc. Additional metal routing in semiconductor devices
US7645653B2 (en) 2006-08-25 2010-01-12 Elpida Memory, Inc. Method for manufacturing a semiconductor device having a polymetal gate electrode structure
JP2009099738A (ja) * 2007-10-16 2009-05-07 Toshiba Corp 半導体装置、半導体装置の製造方法及び半導体記憶装置の製造方法
US9437546B2 (en) 2008-06-30 2016-09-06 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US8803245B2 (en) 2008-06-30 2014-08-12 Mcafee, Inc. Method of forming stacked trench contacts and structures formed thereby
US9293579B2 (en) 2008-06-30 2016-03-22 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
JP2011520297A (ja) * 2008-06-30 2011-07-14 インテル・コーポレーション 積層トレンチコンタクトを形成する方法および当該方法によって形成される構造
US9559060B2 (en) 2008-06-30 2017-01-31 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US9922930B2 (en) 2008-06-30 2018-03-20 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US10297549B2 (en) 2008-06-30 2019-05-21 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US10784201B2 (en) 2008-06-30 2020-09-22 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US11335639B2 (en) 2008-06-30 2022-05-17 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US11721630B2 (en) 2008-06-30 2023-08-08 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
US12142566B2 (en) 2008-06-30 2024-11-12 Intel Corporation Method of forming stacked trench contacts and structures formed thereby
JP2013089712A (ja) * 2011-10-17 2013-05-13 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
KR19990007474A (ko) 1999-01-25
US6072221A (en) 2000-06-06
KR100307124B1 (ko) 2001-10-19

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