KR100307124B1 - 반도체장치및그제조방법 - Google Patents
반도체장치및그제조방법 Download PDFInfo
- Publication number
- KR100307124B1 KR100307124B1 KR1019980025483A KR19980025483A KR100307124B1 KR 100307124 B1 KR100307124 B1 KR 100307124B1 KR 1019980025483 A KR1019980025483 A KR 1019980025483A KR 19980025483 A KR19980025483 A KR 19980025483A KR 100307124 B1 KR100307124 B1 KR 100307124B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- gate
- gate electrode
- insulating film
- contact plug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP97-174199 | 1997-06-30 | ||
| JP9174199A JPH1126757A (ja) | 1997-06-30 | 1997-06-30 | 半導体装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990007474A KR19990007474A (ko) | 1999-01-25 |
| KR100307124B1 true KR100307124B1 (ko) | 2001-10-19 |
Family
ID=15974466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980025483A Expired - Fee Related KR100307124B1 (ko) | 1997-06-30 | 1998-06-30 | 반도체장치및그제조방법 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6072221A (enExample) |
| JP (1) | JPH1126757A (enExample) |
| KR (1) | KR100307124B1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100465380B1 (ko) * | 2000-12-04 | 2005-01-13 | 샤프 가부시키가이샤 | 반도체 장치 및 그의 제조 방법 |
Families Citing this family (58)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861356B2 (en) | 1997-11-05 | 2005-03-01 | Tokyo Electron Limited | Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film |
| US7829144B2 (en) | 1997-11-05 | 2010-11-09 | Tokyo Electron Limited | Method of forming a metal film for electrode |
| JPH11195621A (ja) | 1997-11-05 | 1999-07-21 | Tokyo Electron Ltd | バリアメタル、その形成方法、ゲート電極及びその形成方法 |
| JP3175700B2 (ja) * | 1998-08-24 | 2001-06-11 | 日本電気株式会社 | メタルゲート電界効果トランジスタの製造方法 |
| US6096644A (en) * | 1998-09-08 | 2000-08-01 | Advanced Micro Devices, Inc. | Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides |
| US6432803B1 (en) * | 1998-12-14 | 2002-08-13 | Matsushita Electric Industrial Co., Inc. | Semiconductor device and method of fabricating the same |
| KR20010003682A (ko) * | 1999-06-24 | 2001-01-15 | 김영환 | 자기정렬식 게이트전극 형성방법 |
| KR100345069B1 (ko) * | 1999-06-30 | 2002-07-19 | 주식회사 하이닉스반도체 | 반도체 소자의 폴리실리콘 플러그 형성방법 |
| KR100338104B1 (ko) * | 1999-06-30 | 2002-05-24 | 박종섭 | 반도체 소자의 제조 방법 |
| JP2001102580A (ja) | 1999-09-30 | 2001-04-13 | Nec Corp | 半導体装置及びその製造方法 |
| JP2001127169A (ja) | 1999-10-27 | 2001-05-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| KR100356136B1 (ko) | 1999-12-23 | 2002-10-19 | 동부전자 주식회사 | 반도체 장치 제조 방법 |
| KR100314473B1 (ko) | 1999-12-23 | 2001-11-15 | 한신혁 | 반도체 소자 제조 방법 |
| KR100433093B1 (ko) * | 1999-12-31 | 2004-05-27 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
| US6445050B1 (en) | 2000-02-08 | 2002-09-03 | International Business Machines Corporation | Symmetric device with contacts self aligned to gate |
| KR100350056B1 (ko) * | 2000-03-09 | 2002-08-24 | 삼성전자 주식회사 | 다마신 게이트 공정에서 자기정렬콘택패드 형성 방법 |
| KR100366617B1 (ko) * | 2000-03-13 | 2003-01-09 | 삼성전자 주식회사 | 자기 정렬 콘택홀 제조 방법 |
| KR100456319B1 (ko) * | 2000-05-19 | 2004-11-10 | 주식회사 하이닉스반도체 | 폴리머와 산화막의 연마 선택비 차이를 이용한 반도체소자의 게이트 형성 방법 |
| KR100400030B1 (ko) * | 2000-06-05 | 2003-09-29 | 삼성전자주식회사 | 금속막의 화학 및 기계적 연마용 슬러리 및 그 제조방법과상기 슬러리를 이용한 반도체 소자의 금속 배선 형성 방법 |
| FR2810157B1 (fr) * | 2000-06-09 | 2002-08-16 | Commissariat Energie Atomique | Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene |
| JP2002043544A (ja) | 2000-07-21 | 2002-02-08 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| KR100643571B1 (ko) * | 2000-12-30 | 2006-11-10 | 주식회사 하이닉스반도체 | 금속 대머신 게이트 형성방법 |
| JP3539491B2 (ja) * | 2001-02-26 | 2004-07-07 | シャープ株式会社 | 半導体装置の製造方法 |
| JP2002261277A (ja) | 2001-03-06 | 2002-09-13 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6531324B2 (en) * | 2001-03-28 | 2003-03-11 | Sharp Laboratories Of America, Inc. | MFOS memory transistor & method of fabricating same |
| KR100745951B1 (ko) * | 2001-06-29 | 2007-08-02 | 주식회사 하이닉스반도체 | 금속 게이트 제조 방법 |
| JP3746968B2 (ja) * | 2001-08-29 | 2006-02-22 | 東京エレクトロン株式会社 | 絶縁膜の形成方法および形成システム |
| US6673664B2 (en) * | 2001-10-16 | 2004-01-06 | Sharp Laboratories Of America, Inc. | Method of making a self-aligned ferroelectric memory transistor |
| JP2003224269A (ja) * | 2001-10-26 | 2003-08-08 | Hewlett Packard Co <Hp> | 集積回路を製造するための装置および方法 |
| US6740536B2 (en) * | 2001-10-26 | 2004-05-25 | Hewlett-Packard Develpment Corporation, L.P. | Devices and methods for integrated circuit manufacturing |
| KR100444301B1 (ko) * | 2001-12-29 | 2004-08-16 | 주식회사 하이닉스반도체 | 질화막 cmp를 이용한 다마신 금속 게이트 형성 방법 |
| KR100574487B1 (ko) * | 2002-07-05 | 2006-04-27 | 주식회사 하이닉스반도체 | 반도체소자의 mos 트랜지스터 제조방법 |
| US20040256671A1 (en) * | 2003-06-17 | 2004-12-23 | Kuo-Tai Huang | Metal-oxide-semiconductor transistor with selective epitaxial growth film |
| US7521368B2 (en) * | 2004-05-07 | 2009-04-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| KR100672153B1 (ko) * | 2005-05-25 | 2007-01-19 | 주식회사 하이닉스반도체 | 텅스텐 게이트 전극을 갖는 반도체 소자의 제조방법 |
| KR100792394B1 (ko) * | 2005-09-28 | 2008-01-09 | 주식회사 하이닉스반도체 | 반도체 소자 제조 방법 |
| TWI322485B (en) * | 2005-10-12 | 2010-03-21 | Hynix Semiconductor Inc | Method for forming contact hole of semiconductor device |
| KR100704380B1 (ko) | 2005-12-06 | 2007-04-09 | 한국전자통신연구원 | 반도체 소자 제조 방법 |
| US7859112B2 (en) * | 2006-01-13 | 2010-12-28 | Micron Technology, Inc. | Additional metal routing in semiconductor devices |
| JP4470182B2 (ja) | 2006-08-25 | 2010-06-02 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
| FR2915023B1 (fr) * | 2007-04-13 | 2009-07-17 | St Microelectronics Crolles 2 | Realisation de contacts auto-positionnes par epitaxie |
| JP2009099738A (ja) * | 2007-10-16 | 2009-05-07 | Toshiba Corp | 半導体装置、半導体装置の製造方法及び半導体記憶装置の製造方法 |
| US8803245B2 (en) | 2008-06-30 | 2014-08-12 | Mcafee, Inc. | Method of forming stacked trench contacts and structures formed thereby |
| US7838373B2 (en) * | 2008-07-30 | 2010-11-23 | Intel Corporation | Replacement spacers for MOSFET fringe capacitance reduction and processes of making same |
| US8035165B2 (en) * | 2008-08-26 | 2011-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a first contact structure in a gate last process |
| US7745275B2 (en) * | 2008-09-10 | 2010-06-29 | Arm Limited | Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region |
| US8946828B2 (en) * | 2010-02-09 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having elevated structure and method of manufacturing the same |
| US8373239B2 (en) | 2010-06-08 | 2013-02-12 | International Business Machines Corporation | Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric |
| US8785322B2 (en) * | 2011-01-31 | 2014-07-22 | International Business Machines Corporation | Devices and methods to optimize materials and properties for replacement metal gate structures |
| DE102011004323B4 (de) * | 2011-02-17 | 2016-02-25 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Halbleiterbauelement mit selbstjustierten Kontaktelementen und Verfahren zu seiner Herstellung |
| US8846513B2 (en) * | 2011-09-23 | 2014-09-30 | Globalfoundries Inc. | Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill |
| JP5863381B2 (ja) * | 2011-10-17 | 2016-02-16 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
| CN105448683B (zh) * | 2014-05-26 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法和电子装置 |
| US10510613B2 (en) | 2018-01-23 | 2019-12-17 | Globalfoundries Inc. | Contact structures |
| US10347541B1 (en) | 2018-04-25 | 2019-07-09 | Globalfoundries Inc. | Active gate contacts and method of fabrication thereof |
| US10553486B1 (en) | 2018-07-27 | 2020-02-04 | Globalfoundries Inc. | Field effect transistors with self-aligned metal plugs and methods |
| US10573753B1 (en) | 2018-09-10 | 2020-02-25 | Globalfoundries Inc. | Oxide spacer in a contact over active gate finFET and method of production thereof |
| US10818548B1 (en) | 2019-05-30 | 2020-10-27 | International Business Machines Corporation | Method and structure for cost effective enhanced self-aligned contacts |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559357A (en) * | 1992-09-21 | 1996-09-24 | Krivokapic; Zoran | Poly LDD self-aligned channel transistors |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01270260A (ja) * | 1988-04-21 | 1989-10-27 | Fujitsu Ltd | 半導体装置およびその製造方法 |
| JP3029653B2 (ja) * | 1990-09-14 | 2000-04-04 | 株式会社東芝 | 半導体装置の製造方法 |
| JP3474589B2 (ja) * | 1992-04-17 | 2003-12-08 | 株式会社デンソー | 相補型misトランジスタ装置 |
| US5455444A (en) * | 1994-04-22 | 1995-10-03 | United Microelectronics Corporation | Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices |
| US5491099A (en) * | 1994-08-29 | 1996-02-13 | United Microelectronics Corporation | Method of making silicided LDD with recess in semiconductor substrate |
| JPH0955499A (ja) * | 1995-08-11 | 1997-02-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| US5567631A (en) * | 1995-11-13 | 1996-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology |
| US5804846A (en) * | 1996-05-28 | 1998-09-08 | Harris Corporation | Process for forming a self-aligned raised source/drain MOS device and device therefrom |
| JP2964960B2 (ja) * | 1996-09-27 | 1999-10-18 | 日本電気株式会社 | 半導体装置およびその製造方法 |
| US5866459A (en) * | 1997-02-20 | 1999-02-02 | National Semiconductor Corporation | Method of fabricating a contact structure for an MOS transistor entirely on isolation oxide |
| US5851883A (en) * | 1997-04-23 | 1998-12-22 | Advanced Micro Devices, Inc. | High density integrated circuit process |
-
1997
- 1997-06-30 JP JP9174199A patent/JPH1126757A/ja active Pending
-
1998
- 1998-06-26 US US09/105,021 patent/US6072221A/en not_active Expired - Fee Related
- 1998-06-30 KR KR1019980025483A patent/KR100307124B1/ko not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559357A (en) * | 1992-09-21 | 1996-09-24 | Krivokapic; Zoran | Poly LDD self-aligned channel transistors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100465380B1 (ko) * | 2000-12-04 | 2005-01-13 | 샤프 가부시키가이샤 | 반도체 장치 및 그의 제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990007474A (ko) | 1999-01-25 |
| US6072221A (en) | 2000-06-06 |
| JPH1126757A (ja) | 1999-01-29 |
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