JPH0344419B2 - - Google Patents

Info

Publication number
JPH0344419B2
JPH0344419B2 JP61193004A JP19300486A JPH0344419B2 JP H0344419 B2 JPH0344419 B2 JP H0344419B2 JP 61193004 A JP61193004 A JP 61193004A JP 19300486 A JP19300486 A JP 19300486A JP H0344419 B2 JPH0344419 B2 JP H0344419B2
Authority
JP
Japan
Prior art keywords
trench
groove
substrate
layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61193004A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62105445A (ja
Inventor
Deiitoritsuhi Beiyaa Kurausu
Josefu Shirubesutori Bikutaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS62105445A publication Critical patent/JPS62105445A/ja
Publication of JPH0344419B2 publication Critical patent/JPH0344419B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates

Landscapes

  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
JP61193004A 1985-10-31 1986-08-20 半導体デバイス構造の形成方法 Granted JPS62105445A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/793,518 US4745081A (en) 1985-10-31 1985-10-31 Method of trench filling
US793518 1985-10-31

Publications (2)

Publication Number Publication Date
JPS62105445A JPS62105445A (ja) 1987-05-15
JPH0344419B2 true JPH0344419B2 (enFirst) 1991-07-05

Family

ID=25160098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61193004A Granted JPS62105445A (ja) 1985-10-31 1986-08-20 半導体デバイス構造の形成方法

Country Status (4)

Country Link
US (2) US4745081A (enFirst)
EP (1) EP0221394B1 (enFirst)
JP (1) JPS62105445A (enFirst)
DE (1) DE3686125T2 (enFirst)

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US4845051A (en) * 1987-10-29 1989-07-04 Siliconix Incorporated Buried gate JFET
US4835115A (en) * 1987-12-07 1989-05-30 Texas Instruments Incorporated Method for forming oxide-capped trench isolation
US4873205A (en) * 1987-12-21 1989-10-10 International Business Machines Corporation Method for providing silicide bridge contact between silicon regions separated by a thin dielectric
JPH01173714A (ja) * 1987-12-21 1989-07-10 Internatl Business Mach Corp <Ibm> ブリツジ接点の形成方法
JPH0656865B2 (ja) * 1988-10-13 1994-07-27 株式会社東芝 高耐圧素子用接着基板
IT1225625B (it) * 1988-11-03 1990-11-22 Sgs Thomson Microelectronics Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos.
US5105253A (en) * 1988-12-28 1992-04-14 Synergy Semiconductor Corporation Structure for a substrate tap in a bipolar structure
JPH02271535A (ja) * 1988-12-28 1990-11-06 Synergy Semiconductor Corp バイポーラ構造における基板タップ及びこの製造方法
US5108946A (en) * 1989-05-19 1992-04-28 Motorola, Inc. Method of forming planar isolation regions
JPH0358484A (ja) * 1989-07-27 1991-03-13 Toshiba Corp 半導体装置とその製造方法
US5223736A (en) * 1989-09-27 1993-06-29 Texas Instruments Incorporated Trench isolation process with reduced topography
US5077228A (en) * 1989-12-01 1991-12-31 Texas Instruments Incorporated Process for simultaneous formation of trench contact and vertical transistor gate and structure
US5159429A (en) * 1990-01-23 1992-10-27 International Business Machines Corporation Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same
US5061652A (en) * 1990-01-23 1991-10-29 International Business Machines Corporation Method of manufacturing a semiconductor device structure employing a multi-level epitaxial structure
JP2641781B2 (ja) * 1990-02-23 1997-08-20 シャープ株式会社 半導体素子分離領域の形成方法
US5296392A (en) * 1990-03-06 1994-03-22 Digital Equipment Corporation Method of forming trench isolated regions with sidewall doping
US5139966A (en) * 1990-04-02 1992-08-18 National Semiconductor Corporation Low resistance silicided substrate contact
JP2757927B2 (ja) * 1990-06-28 1998-05-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体基板上の隔置されたシリコン領域の相互接続方法
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5250461A (en) * 1991-05-17 1993-10-05 Delco Electronics Corporation Method for dielectrically isolating integrated circuits using doped oxide sidewalls
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
JPH0513566A (ja) * 1991-07-01 1993-01-22 Toshiba Corp 半導体装置の製造方法
JPH05211239A (ja) * 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
US5185294A (en) * 1991-11-22 1993-02-09 International Business Machines Corporation Boron out-diffused surface strap process
JP2890380B2 (ja) 1991-11-27 1999-05-10 三菱電機株式会社 半導体装置およびその製造方法
US5236863A (en) * 1992-06-01 1993-08-17 National Semiconductor Corporation Isolation process for VLSI
US5217920A (en) * 1992-06-18 1993-06-08 Motorola, Inc. Method of forming substrate contact trenches and isolation trenches using anodization for isolation
US5494857A (en) * 1993-07-28 1996-02-27 Digital Equipment Corporation Chemical mechanical planarization of shallow trenches in semiconductor substrates
US5346584A (en) * 1993-07-28 1994-09-13 Digital Equipment Corporation Planarization process for IC trench isolation using oxidized polysilicon filler
US5479048A (en) * 1994-02-04 1995-12-26 Analog Devices, Inc. Integrated circuit chip supported by a handle wafer and provided with means to maintain the handle wafer potential at a desired level
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
US5872044A (en) * 1994-06-15 1999-02-16 Harris Corporation Late process method for trench isolation
JPH08195433A (ja) * 1995-01-19 1996-07-30 Toshiba Corp 半導体装置及びその製造方法
JP3360970B2 (ja) * 1995-05-22 2003-01-07 株式会社東芝 半導体装置の製造方法
US5920108A (en) * 1995-06-05 1999-07-06 Harris Corporation Late process method and apparatus for trench isolation
US5859466A (en) 1995-06-07 1999-01-12 Nippon Steel Semiconductor Corporation Semiconductor device having a field-shield device isolation structure and method for making thereof
KR100192178B1 (ko) * 1996-01-11 1999-06-15 김영환 반도체 소자의 아이솔레이션 방법
US5817560A (en) * 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
FR2761810A1 (fr) * 1997-02-28 1998-10-09 Int Rectifier Corp Dispositif a semi-conducteur et son procede de fabrication
US5851900A (en) * 1997-04-28 1998-12-22 Mosel Vitelic Inc. Method of manufacturing a shallow trench isolation for a semiconductor device
AT2173U1 (de) * 1997-06-19 1998-05-25 Austria Mikrosysteme Int Verfahren zur herstellung von begrenzten, dotierten teilgebieten in einem substratmaterial aus monokristallinem silizium
CN1263637A (zh) 1997-07-11 2000-08-16 艾利森电话股份有限公司 制作用于射频的集成电路器件的工艺
US6251734B1 (en) 1998-07-01 2001-06-26 Motorola, Inc. Method for fabricating trench isolation and trench substrate contact
US6251769B1 (en) * 1999-07-02 2001-06-26 United Microelectronics Corp Method of manufacturing contact pad
US6388305B1 (en) * 1999-12-17 2002-05-14 International Business Machines Corporation Electrically programmable antifuses and methods for forming the same
US6627949B2 (en) * 2000-06-02 2003-09-30 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
KR100389923B1 (ko) 2001-01-16 2003-07-04 삼성전자주식회사 트렌치 소자 분리구조를 가지는 반도체 소자 및 트렌치소자 분리 방법
DE10110974C2 (de) * 2001-03-07 2003-07-24 Infineon Technologies Ag Verfahren zum Verbreitern eines aktiven Halbleitergebiets auf einem Halbleitersubstrat
JP2002359290A (ja) 2001-03-27 2002-12-13 Matsushita Electric Ind Co Ltd 半導体集積装置
US6621136B2 (en) 2001-09-28 2003-09-16 Semiconductor Components Industries Llc Semiconductor device having regions of low substrate capacitance
US6696349B2 (en) * 2001-11-13 2004-02-24 Infineon Technologies Richmond Lp STI leakage reduction
KR100400254B1 (ko) * 2001-12-18 2003-10-01 주식회사 하이닉스반도체 반도체 소자의 제조방법
US6724798B2 (en) 2001-12-31 2004-04-20 Honeywell International Inc. Optoelectronic devices and method of production
US6994903B2 (en) * 2002-01-03 2006-02-07 International Business Machines Corp. Hybrid substrate and method for fabricating the same
EP1641045A3 (en) * 2002-11-12 2006-06-07 Micron Technology, Inc. Grounded gate and isolation techniques for reducing dark current in CMOS image sensors
US6646320B1 (en) * 2002-11-21 2003-11-11 National Semiconductor Corporation Method of forming contact to poly-filled trench isolation region
DE10320414A1 (de) * 2003-05-07 2004-12-23 Infineon Technologies Ag Halbleiteranordnung mit Schutzanordnung zur Verhinderung einer Diffusion von Minoritätsladungsträgern
US6818950B1 (en) * 2003-05-13 2004-11-16 Micrel, Inc. Increasing switching speed of geometric construction gate MOSFET structures
US7410864B2 (en) * 2004-04-23 2008-08-12 Infineon Technologies Ag Trench and a trench capacitor and method for forming the same
DE102004028679A1 (de) * 2004-06-14 2006-01-05 Infineon Technologies Ag Isolationsgrabenanordnung
US7468307B2 (en) 2005-06-29 2008-12-23 Infineon Technologies Ag Semiconductor structure and method
US7982284B2 (en) 2006-06-28 2011-07-19 Infineon Technologies Ag Semiconductor component including an isolation structure and a contact to the substrate
DE102006029701B4 (de) * 2006-06-28 2017-06-01 Infineon Technologies Ag Halbleiterbauteil sowie Verfahren zur Herstellung eines Halbleiterbauteils
DE102006046377A1 (de) * 2006-09-29 2008-04-03 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen
DE102007018098B4 (de) * 2007-04-17 2016-06-16 Austriamicrosystems Ag Verfahren zum Herstellen eines Halbleiterkörpers mit einem Graben und Halbleiterkörper mit einem Graben
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
DE102010006996B4 (de) 2010-02-05 2017-08-24 Austriamicrosystems Ag Verfahren zur Herstellung eines Halbleiterbauelements
US8492260B2 (en) * 2010-08-30 2013-07-23 Semionductor Components Industries, LLC Processes of forming an electronic device including a feature in a trench
US8647945B2 (en) 2010-12-03 2014-02-11 International Business Machines Corporation Method of forming substrate contact for semiconductor on insulator (SOI) substrate
US8673737B2 (en) * 2011-10-17 2014-03-18 International Business Machines Corporation Array and moat isolation structures and method of manufacture
US20160043218A1 (en) * 2014-08-05 2016-02-11 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
US9812354B2 (en) 2015-05-15 2017-11-07 Semiconductor Components Industries, Llc Process of forming an electronic device including a material defining a void
CN109994537B (zh) * 2017-12-29 2022-09-06 联华电子股份有限公司 半导体元件及其制作方法

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Also Published As

Publication number Publication date
US4745081A (en) 1988-05-17
JPS62105445A (ja) 1987-05-15
EP0221394B1 (en) 1992-07-22
EP0221394A3 (en) 1989-04-26
DE3686125T2 (de) 1993-03-11
EP0221394A2 (en) 1987-05-13
DE3686125D1 (de) 1992-08-27
US4924284A (en) 1990-05-08

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