JP7165151B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7165151B2 JP7165151B2 JP2020024854A JP2020024854A JP7165151B2 JP 7165151 B2 JP7165151 B2 JP 7165151B2 JP 2020024854 A JP2020024854 A JP 2020024854A JP 2020024854 A JP2020024854 A JP 2020024854A JP 7165151 B2 JP7165151 B2 JP 7165151B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
Description
100:半導体装置
110:入出力回路
120、130、140:内部回路
150:コントローラ
160:DPD判定部
162:計測部
164:移行時間検出部
166:DPD信号生成部
200-1:内部電圧生成回路
210:ロジック
220:タイマ
230:ロジック
CMP、CMP1、CMP2:比較器
LAD:抵抗ラダー
Claims (11)
- 外部からの入力信号に応答して動作可能な半導体集積回路と、
第1の供給電圧に基づき第2の供給電圧を生成する電圧生成回路とを含み、
前記電圧生成回路は、半導体装置がスタンバイモードに突入した時点からの時間を計測する計測手段と、前記計測手段により計測された計測時間の経過に応答して、前記スタンバイモードの消費電力をさらに低減させるための複数のパワーダウンイネーブル信号を生成する生成手段とを有し、
前記電圧生成回路はさらに、
第1の供給電圧を供給する第1のノードと、
第2の供給電圧を負荷に供給する第2のノードと、
前記第1のノードと前記第2のノードとの間に接続され、制御信号に応答して前記第1のノードと前記第2のノードの接続または非接続を行う接続回路と、
前記第2のノードと基準電位との間に接続された抵抗ラダーと、
前記第1のノードと前記第2のノードとが非接続のとき、前記第2のノードと前記基準電位との間に生成されるRC時定数に基づきパルス信号を生成するパルス生成回路と、
前記パルス信号に基づき前記制御信号を生成するロジック回路と、
前記パルス信号に基づき生成されたクロックを計数するカウンタと、
前記カウンタのカウント値に基づきパワーダウンイネーブル信号を生成する生成回路とを含む、半導体装置。 - 前記生成手段は、少なくとも第1および第2のパワーダウンイネーブル信号を生成し、
第1のパワーダウンイネーブル信号は、前記計測時間が第1の決められた時間に到達したときに生成され、第2のパワーダウンイネーブル信号は、前記計測時間が第1の決められた時間よりも長い第2の決められた時間に到達したときに生成される、請求項1に記載の半導体装置。 - 前記生成手段は、少なくとも第1および第2のパワーダウンイネーブル信号を生成し、前記第1のパワーダウンイネーブル信号は、前記半導体集積回路の第1の内部回路に提供され、前記第2のパワーダウンイネーブル信号は、前記半導体集積回路の第2の内部回路に提供され、
第1および第2の内部回路への電力供給は、前記第1および第2のパワーダウンイネーブル信号に応答して遮断される、請求項1に記載の半導体装置。 - 前記電圧生成回路は、複数の電圧生成回路を含み、複数の電圧生成回路が複数のパワーダウンイネーブル信号を生成する、請求項1に記載の半導体装置。
- 前記半導体集積回路は、複数のパワーダウンイネーブル信号に応答して電力供給が遮断される内部回路と、スタンバイモード時に動作し、前記複数のパワーダウンイネーブル信号により電力供給が遮断されないスタンバイ用内部回路とを含む、請求項1ないし4いずれか1つに記載の半導体装置。
- 前記スタンバイ用内部回路は、揮発性記憶回路を含む、請求項5に記載の半導体装置。
- 前記生成回路は、前記カウンタのカウント値に基づき複数のパワーダウンイネーブル信号を生成する、請求項1に記載の半導体装置。
- 前記パルス生成回路は、前記抵抗ラダーで生成される第1の電圧と基準電圧とを比較する第1の比較器と、前記抵抗ラダーで生成される前記第1の電圧よりも小さい第2の電圧と基準電圧とを比較する第2の比較器とを含み、第1および第2の比較器の比較結果に基づき前記パルス信号を生成する、請求項1に記載の半導体装置。
- 前記接続回路は、前記制御信号がゲートに印加されるPMOSトランジスタを含み、
前記ロジック回路は、前記RC時定数で規定される時間が経過したとき、前記制御信号をLレベルに遷移させる、請求項1に記載の半導体装置。 - 前記ロジック回路は、前記生成回路で生成されたパワーダウンイネーブル信号をフィードバック入力し、当該パワーダウンイネーブル信号に応答して前記接続回路を非接続にする、請求項1に記載の半導体装置。
- 前記半導体集積回路は、フラッシュメモリに関する回路を含み、前記スタンバイモードは、フラッシュメモリのビジー信号またはレディ信号に応答して移行する、請求項1に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020024854A JP7165151B2 (ja) | 2020-02-18 | 2020-02-18 | 半導体装置 |
TW109146184A TWI740757B (zh) | 2020-02-18 | 2020-12-25 | 半導體裝置 |
CN202110043229.3A CN113345483B (zh) | 2020-02-18 | 2021-01-13 | 半导体装置 |
US17/148,587 US11496118B2 (en) | 2020-02-18 | 2021-01-14 | Semiconductor device |
KR1020210009415A KR102444405B1 (ko) | 2020-02-18 | 2021-01-22 | 반도체 장치 |
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JP2020024854A JP7165151B2 (ja) | 2020-02-18 | 2020-02-18 | 半導体装置 |
Publications (2)
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JP2021131916A JP2021131916A (ja) | 2021-09-09 |
JP7165151B2 true JP7165151B2 (ja) | 2022-11-02 |
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US (1) | US11496118B2 (ja) |
JP (1) | JP7165151B2 (ja) |
KR (1) | KR102444405B1 (ja) |
CN (1) | CN113345483B (ja) |
TW (1) | TWI740757B (ja) |
Cited By (1)
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2020
- 2020-02-18 JP JP2020024854A patent/JP7165151B2/ja active Active
- 2020-12-25 TW TW109146184A patent/TWI740757B/zh active
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2021
- 2021-01-13 CN CN202110043229.3A patent/CN113345483B/zh active Active
- 2021-01-14 US US17/148,587 patent/US11496118B2/en active Active
- 2021-01-22 KR KR1020210009415A patent/KR102444405B1/ko active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013186920A (ja) | 2012-03-08 | 2013-09-19 | Toshiba Corp | 不揮発性半導体記憶装置及びメモリシステム |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7397514B2 (ja) | 2022-01-24 | 2023-12-13 | 介▲隆▼興齒輪股▲ふん▼有限公司 | 内装変速機のギアシフト制御機構 |
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Publication number | Publication date |
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JP2021131916A (ja) | 2021-09-09 |
US20210257997A1 (en) | 2021-08-19 |
CN113345483A (zh) | 2021-09-03 |
TWI740757B (zh) | 2021-09-21 |
KR20210105809A (ko) | 2021-08-27 |
US11496118B2 (en) | 2022-11-08 |
CN113345483B (zh) | 2024-03-26 |
KR102444405B1 (ko) | 2022-09-19 |
TW202133167A (zh) | 2021-09-01 |
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