JP6828449B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP6828449B2
JP6828449B2 JP2017006002A JP2017006002A JP6828449B2 JP 6828449 B2 JP6828449 B2 JP 6828449B2 JP 2017006002 A JP2017006002 A JP 2017006002A JP 2017006002 A JP2017006002 A JP 2017006002A JP 6828449 B2 JP6828449 B2 JP 6828449B2
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Prior art keywords
insulating film
interlayer insulating
semiconductor
contact hole
semiconductor device
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Japanese (ja)
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JP2018117016A5 (enExample
JP2018117016A (ja
Inventor
泰 浦上
泰 浦上
武寛 加藤
武寛 加藤
佐智子 青井
佐智子 青井
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Denso Corp
Toyota Central R&D Labs Inc
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Denso Corp
Toyota Central R&D Labs Inc
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Priority to JP2017006002A priority Critical patent/JP6828449B2/ja
Priority to PCT/JP2018/001260 priority patent/WO2018135541A1/ja
Priority to CN201880006937.6A priority patent/CN110235229B/zh
Publication of JP2018117016A publication Critical patent/JP2018117016A/ja
Publication of JP2018117016A5 publication Critical patent/JP2018117016A5/ja
Priority to US16/511,345 priority patent/US10923395B2/en
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    • H—ELECTRICITY
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP2017006002A 2017-01-17 2017-01-17 半導体装置およびその製造方法 Active JP6828449B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017006002A JP6828449B2 (ja) 2017-01-17 2017-01-17 半導体装置およびその製造方法
PCT/JP2018/001260 WO2018135541A1 (ja) 2017-01-17 2018-01-17 半導体装置およびその製造方法
CN201880006937.6A CN110235229B (zh) 2017-01-17 2018-01-17 半导体装置及其制造方法
US16/511,345 US10923395B2 (en) 2017-01-17 2019-07-15 Semiconductor device and manufacturing method of semiconductor device

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JP2017006002A JP6828449B2 (ja) 2017-01-17 2017-01-17 半導体装置およびその製造方法

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JP2018117016A JP2018117016A (ja) 2018-07-26
JP2018117016A5 JP2018117016A5 (enExample) 2019-04-25
JP6828449B2 true JP6828449B2 (ja) 2021-02-10

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JP (1) JP6828449B2 (enExample)
CN (1) CN110235229B (enExample)
WO (1) WO2018135541A1 (enExample)

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JPWO2020031971A1 (ja) * 2018-08-07 2021-08-10 ローム株式会社 ＳｉＣ半導体装置
WO2020032206A1 (ja) 2018-08-10 2020-02-13 ローム株式会社 ＳｉＣ半導体装置
CN112567531A (zh) 2018-08-10 2021-03-26 罗姆股份有限公司 SiC半导体装置
JP7188230B2 (ja) * 2019-03-28 2022-12-13 株式会社デンソー 半導体装置
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JP7081564B2 (ja) * 2019-04-24 2022-06-07 株式会社デンソー 半導体装置とその製造方法
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JP7404722B2 (ja) * 2019-09-06 2023-12-26 富士電機株式会社 半導体装置
JP7476502B2 (ja) * 2019-09-06 2024-05-01 富士電機株式会社 半導体装置
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JP7129397B2 (ja) * 2019-12-06 2022-09-01 ローム株式会社 ＳｉＣ半導体装置
JP7129436B2 (ja) * 2020-02-17 2022-09-01 ローム株式会社 ＳｉＣ半導体装置
JP7129437B2 (ja) * 2020-02-17 2022-09-01 ローム株式会社 ＳｉＣ半導体装置
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JP7697255B2 (ja) * 2021-04-27 2025-06-24 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
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CN114583013A (zh) * 2022-03-10 2022-06-03 常州时创能源股份有限公司 一种bsg去除方法
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JP7765881B2 (ja) * 2022-09-09 2025-11-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
TWI817895B (zh) * 2023-01-30 2023-10-01 李羿軒 具有創新邊緣終端部的半導體裝置
JP7834044B2 (ja) 2023-02-24 2026-03-23 三菱電機株式会社 半導体装置及び半導体装置の製造方法
WO2025052689A1 (ja) * 2023-09-04 2025-03-13 株式会社 東芝 半導体装置
CN119170507B (zh) * 2024-11-19 2025-03-21 芯联越州集成电路制造（绍兴）有限公司 一种半导体器件及其制造方法、电子装置

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JP6245723B2 (ja) 2012-04-27 2017-12-13 富士電機株式会社 炭化珪素半導体装置の製造方法
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JP6160477B2 (ja) * 2013-12-25 2017-07-12 トヨタ自動車株式会社 半導体装置
JP6344483B2 (ja) * 2014-11-17 2018-06-20 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6406361B2 (ja) * 2015-02-03 2018-10-17 富士電機株式会社 半導体装置及びその製造方法
JP6409681B2 (ja) 2015-05-29 2018-10-24 株式会社デンソー 半導体装置およびその製造方法

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