CN110235229B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN110235229B CN110235229B CN201880006937.6A CN201880006937A CN110235229B CN 110235229 B CN110235229 B CN 110235229B CN 201880006937 A CN201880006937 A CN 201880006937A CN 110235229 B CN110235229 B CN 110235229B
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- insulating film
- interlayer insulating
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- H—ELECTRICITY
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- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
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- H10D12/031—Manufacture or treatment of IGBTs
- H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
- H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D64/251—Source or drain electrodes for field-effect devices
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
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- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
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- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/48—Insulating materials thereof
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017006002A JP6828449B2 (ja) | 2017-01-17 | 2017-01-17 | 半導体装置およびその製造方法 |
| JP2017-006002 | 2017-01-17 | ||
| PCT/JP2018/001260 WO2018135541A1 (ja) | 2017-01-17 | 2018-01-17 | 半導体装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110235229A CN110235229A (zh) | 2019-09-13 |
| CN110235229B true CN110235229B (zh) | 2022-08-12 |
Family
ID=62908552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880006937.6A Active CN110235229B (zh) | 2017-01-17 | 2018-01-17 | 半导体装置及其制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10923395B2 (enExample) |
| JP (1) | JP6828449B2 (enExample) |
| CN (1) | CN110235229B (enExample) |
| WO (1) | WO2018135541A1 (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019069580A1 (ja) * | 2017-10-05 | 2019-04-11 | 富士電機株式会社 | 半導体装置 |
| WO2020031971A1 (ja) * | 2018-08-07 | 2020-02-13 | ローム株式会社 | SiC半導体装置 |
| US11626490B2 (en) | 2018-08-10 | 2023-04-11 | Rohm Co., Ltd. | SiC semiconductor device |
| WO2020032190A1 (ja) | 2018-08-10 | 2020-02-13 | ローム株式会社 | SiC半導体装置 |
| JP7188230B2 (ja) * | 2019-03-28 | 2022-12-13 | 株式会社デンソー | 半導体装置 |
| JP7443673B2 (ja) * | 2019-04-15 | 2024-03-06 | 富士電機株式会社 | 炭化珪素半導体装置 |
| JP7081564B2 (ja) * | 2019-04-24 | 2022-06-07 | 株式会社デンソー | 半導体装置とその製造方法 |
| JP7472435B2 (ja) | 2019-05-13 | 2024-04-23 | 富士電機株式会社 | 半導体モジュールの製造方法 |
| JP7404722B2 (ja) * | 2019-09-06 | 2023-12-26 | 富士電機株式会社 | 半導体装置 |
| JP7476502B2 (ja) | 2019-09-06 | 2024-05-01 | 富士電機株式会社 | 半導体装置 |
| CN114430861A (zh) * | 2019-09-30 | 2022-05-03 | 罗姆股份有限公司 | 半导体装置 |
| JP7129397B2 (ja) * | 2019-12-06 | 2022-09-01 | ローム株式会社 | SiC半導体装置 |
| JP7129437B2 (ja) * | 2020-02-17 | 2022-09-01 | ローム株式会社 | SiC半導体装置 |
| JP7129436B2 (ja) * | 2020-02-17 | 2022-09-01 | ローム株式会社 | SiC半導体装置 |
| CN115867926A (zh) * | 2020-08-12 | 2023-03-28 | 应用材料公司 | 使用机器学习的工具漂移补偿 |
| CN118738128A (zh) * | 2020-09-17 | 2024-10-01 | 罗姆股份有限公司 | 半导体装置 |
| JP7697255B2 (ja) * | 2021-04-27 | 2025-06-24 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
| US12490451B2 (en) * | 2022-03-02 | 2025-12-02 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a component structure adjacent to a trench |
| CN114583013A (zh) * | 2022-03-10 | 2022-06-03 | 常州时创能源股份有限公司 | 一种bsg去除方法 |
| JP7765881B2 (ja) * | 2022-09-09 | 2025-11-07 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US20240290837A1 (en) | 2023-02-24 | 2024-08-29 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
| CN119968936A (zh) * | 2023-09-04 | 2025-05-09 | 株式会社东芝 | 半导体装置 |
| CN119170507B (zh) * | 2024-11-19 | 2025-03-21 | 芯联越州集成电路制造(绍兴)有限公司 | 一种半导体器件及其制造方法、电子装置 |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0456222A (ja) * | 1990-06-25 | 1992-02-24 | Matsushita Electron Corp | 半導体装置の製造方法 |
| JPH06177129A (ja) * | 1992-12-09 | 1994-06-24 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
| US5716891A (en) * | 1994-06-30 | 1998-02-10 | Nec Corporation | Fabrication process of semiconductor device |
| JP2002134607A (ja) * | 2000-10-20 | 2002-05-10 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| CN101088155A (zh) * | 2004-10-25 | 2007-12-12 | 斯班逊有限公司 | 半导体装置及其制造方法 |
| JP2014027076A (ja) * | 2012-07-26 | 2014-02-06 | Renesas Electronics Corp | 半導体装置 |
| WO2016080269A1 (ja) * | 2014-11-17 | 2016-05-26 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
| WO2016125490A1 (ja) * | 2015-02-03 | 2016-08-11 | 富士電機株式会社 | 半導体装置及びその製造方法 |
| JP2016225455A (ja) * | 2015-05-29 | 2016-12-28 | 株式会社デンソー | 半導体装置およびその製造方法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582781A (ja) * | 1991-09-24 | 1993-04-02 | Nec Yamagata Ltd | 半導体集積回路装置 |
| JP3543504B2 (ja) * | 1996-08-06 | 2004-07-14 | ソニー株式会社 | 半導体装置の製造方法 |
| JP2007096263A (ja) | 2005-08-31 | 2007-04-12 | Denso Corp | 炭化珪素半導体装置およびその製造方法。 |
| KR100872981B1 (ko) * | 2007-07-19 | 2008-12-08 | 주식회사 동부하이텍 | 반도체 소자의 제조방법 |
| EP2091083A3 (en) | 2008-02-13 | 2009-10-14 | Denso Corporation | Silicon carbide semiconductor device including a deep layer |
| JP2010165778A (ja) * | 2009-01-14 | 2010-07-29 | Sharp Corp | 半導体装置の製造方法 |
| JP5813303B2 (ja) | 2009-11-20 | 2015-11-17 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理方法および基板処理装置 |
| JP5770892B2 (ja) * | 2009-11-20 | 2015-08-26 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理方法および基板処理装置 |
| KR101995682B1 (ko) * | 2011-03-18 | 2019-07-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 산화물 반도체막, 반도체 장치, 및 반도체 장치의 제작 방법 |
| JP2013041919A (ja) | 2011-08-12 | 2013-02-28 | Renesas Electronics Corp | 半導体装置の製造方法 |
| JP6245723B2 (ja) | 2012-04-27 | 2017-12-13 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
| JP6160477B2 (ja) * | 2013-12-25 | 2017-07-12 | トヨタ自動車株式会社 | 半導体装置 |
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2017
- 2017-01-17 JP JP2017006002A patent/JP6828449B2/ja active Active
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2018
- 2018-01-17 CN CN201880006937.6A patent/CN110235229B/zh active Active
- 2018-01-17 WO PCT/JP2018/001260 patent/WO2018135541A1/ja not_active Ceased
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2019
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| CN110235229A (zh) | 2019-09-13 |
| US20190341308A1 (en) | 2019-11-07 |
| WO2018135541A1 (ja) | 2018-07-26 |
| US10923395B2 (en) | 2021-02-16 |
| JP2018117016A (ja) | 2018-07-26 |
| JP6828449B2 (ja) | 2021-02-10 |
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