JP6745894B2 - 導電性構造、導電性構造を含むシステムと装置および関連する方法 - Google Patents
導電性構造、導電性構造を含むシステムと装置および関連する方法 Download PDFInfo
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Description
本願は、「CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS」と題して2016年3月11日に出願された米国特許出願第15/068,329号に基づく出願日の利益を請求する。
本開示の実施形態は、導電性構造(例えば、細長い階段状導電性構造)であって導電性構造の少なくとも一部を通って延びる複数の接点(コンタクト)を有するもの、このような導電性構造を含む装置、このような導電性構造を含むシステム、このような導電性構造
を製造する方法、および細長い階段状導電性構造のための電気接続を形成する方法に関する。
例えば、金属材料(例えば、W、Ni、窒化タンタル(TaN)、Pt、窒化タングステン(WN)、Au、窒化チタン(TiN)、または窒化チタンアルミニウム(TiAlN))、ポリシリコン、他の導電性材料またはこれらの組み合わせの材料から作られ得る。
含む、半導体系材料を含むあらゆる構造を含み得る。基板104は、例えば、従来の基板だけでなく他のバルク半導体基板でもよく、限定ではなく例として、シリコンオンインシュレーター(SOI)基板、シリコンオンサファイア(SOS)基板、またはシリコンのエピタキシャル層が別の材料によって支持されているもの、を含んでよい。さらに、以下の説明で「基板」と言及されている場合には、基板内または上に回路やデバイスの素子や部品を少なくとも部分的に形成するために、その前の処理工程の段階のものが用いられていてもよい。いくつかの実施形態において、基板104は、例えば、電子デバイスまたは半導体デバイス102(図1)の他の部分等を含む、導電性構造100が上方(例えば、上)に形成され得るあらゆる構造を含み得る。
/または物理的に)分離または絶縁されている。明瞭性のために、導電性材料103と絶縁性材料105の二組(例えば、段)の一部のみが明瞭性のために示されている。
いくつかの実施形態においては、内側スタックスロット要素238は、階段状構造206、208、210のサブブロック(例えば、副段、副階層、サブプレート)を画定するよう機能してもよい。
が確実に半導体デバイス202と電子通信を続けられるようにすることができる。
Claims (25)
- 導電性構造であって、
前記導電性構造の長さに沿って設置される複数の階段状構造であって、それぞれの階段状構造は少なくとも二つの導電性の段を含み、前記少なくとも二つの導電性の段のそれぞれの導電性の段は絶縁性材料によって前記少なくとも二つの導電性の段のうちの隣り合う導電性の段から少なくとも部分的に分離される、複数の階段状構造と、
少なくとも一つのランディングであって、該少なくとも一つのランディングの各々が、前記導電性構造を通って延びる複数のビアを含み、前記少なくとも一つのランディングが、前記複数の階段状構造のうちの第一の階段状構造と、前記第一の階段状構造の隣りに設置される前記複数の階段状構造のうちの第二の階段状構造との間に設置される、少なくとも一つのランディングと、
複数のアクセス線であって、該複数のアクセス線のうちの少なくとも幾つかが、前記階段状構造の前記少なくとも二つの導電性の段のうちの一つの導電性の段の導電性部分から、前記少なくとも一つのランディングまで延びて、且つ、前記複数のビアのそれぞれまで延びる、複数のアクセス線と、
を含む導電性構造。 - それぞれのアクセス線が前記階段状構造の少なくとも二つの導電性の段のうち一つの導電性の段の導電性部分から前記複数のビアのうちの一つのビアまで延びる、請求項1に記載の導電性構造。
- 少なくとも一対の追加の階段状構造と少なくとも一つの追加のランディングを更に含み、前記少なくとも一対の追加の階段状構造のそれぞれの追加の階段状構造は、前記少なくとも一つの追加のランディングを間にして、前記少なくとも一対の追加の階段状構造の別の階段状構造とは反対側にある、請求項1に記載の導電性構造。
- 前記複数の階段状構造のうちの少なくとも一つの階段状構造には前記少なくとも一つの階段状構造の導電性の段に接続されるアクセス線がない、請求項1に記載の導電性構造。
- 前記少なくとも一つのランディングは複数のランディングを含み、前記複数のランディングのうちのそれぞれのランディングは一対の前記階段状構造の間に設置される、請求項1に記載の導電性構造。
- 前記少なくとも一つのランディングは交互になっている第一の材料及び第二の材料の積層によって画定され、前記第一の材料と前記第二の材料はそれぞれ絶縁性材料を含む、請求項1に記載の導電性構造。
- 前記少なくとも一つのランディングは交互になっている第一の材料及び第二の材料の積層によって画定され、前記第一の材料は導電性材料を含み、前記第二の材料は絶縁性材料を含む、請求項1に記載の導電性構造。
- 前記複数のビアのうちの少なくとも幾つかを少なくとも部分的に囲み且つ前記複数のビアのうちの前記少なくとも幾つかを前記少なくとも一つのランディングの前記導電性材料から絶縁する絶縁性ライナーを更に含む、請求項7に記載の導電性構造。
- 前記複数のビアのうちの前記少なくとも幾つかは、前記複数の階段状構造及び前記少なくとも一つのランディングの下にある少なくとも一つの制御部と動作可能に結合される、請求項1に記載の導電性構造。
- 前記複数の階段状構造のうち少なくともいくつかはそれぞれワード線プレート構造を含む、請求項1に記載の導電性構造。
- 前記複数の階段状構造のうちの一つの階段状構造がドレイン側選択ゲート(SGD)構造を含む、請求項1に記載の導電性構造。
- 前記導電性構造の長さに沿って延びる複数のスタックスロット要素を更に含む、請求項1から請求項11の何れか1項に記載の導電性構造。
- 前記複数のスタックスロット要素は
前記導電性構造の前記長さの大部分に沿って連続的に延びる複数の外側スタックスロット要素と、
前記導電性構造の前記長さに沿って不連続的に延びる複数の内側スタックスロット要素と、
を含む、請求項12に記載の導電性構造。 - 前記複数の内側スタックスロット要素は前記複数の階段状構造の近くに設置される、請求項13に記載の導電性構造。
- 前記少なくとも一つのランディングには前記複数の内側スタックスロット要素がない、請求項14に記載の導電性構造。
- 前記複数のスタックスロット要素は、置換ゲート工程中に堆積された、導電性材料の上に設置される絶縁性材料を含む、請求項13に記載の導電性構造。
- 複数のメモリセルのアレイと、
前記アレイの複数のメモリセルを選択するために前記複数のメモリセルのアレイの隣に設置されて前記複数のメモリセルのアレイと電気的に通じている請求項1から請求項16のいずれか1項に記載の導電性構造と、
を含む装置。 - 導電性構造を形成する方法であって、
二つの階段状構造の間に画定される前記導電性構造のランディングのところで、材料の積層を通る複数の開口部を形成することであって、前記二つの階段状構造は、半導体デバイスの片側に設置され且つ該半導体デバイスと電気的に通じている、ことと、
前記ランディングのところで、前記材料の積層中の前記複数の開口部内に複数のコンタクトを形成することと、
前記ランディングのところで、前記二つの階段状構造の少なくとも一つの段の導電性部分と前記複数のコンタクトのうちの少なくとも一つのコンタクトとを電気的に結合することと、
を含む方法。 - 前記材料の積層を、交互になっている絶縁性材料と導電性材料とで形成すること、を更に含む、請求項18に記載の方法。
- 前記複数の開口部のうちのそれぞれの開口部内にライナーを形成して、前記開口部の中のコンタクトを囲むこと、を更に含む、請求項19に記載の方法。
- 前記材料の積層を、交互になっている、第一の絶縁性材料及び第二の犠牲絶縁性材料を含む複数の絶縁性材料で形成すること、を更に含む、請求項18に記載の方法。
- 前記材料の積層を通る開口部を形成することと、
前記第一の絶縁性材料の下にある前記第二の犠牲絶縁性材料の体積のうち、前記開口部の隣にある前記第二の犠牲絶縁性材料の一部を除去することと、
前記開口部内と、前記第二の犠牲絶縁性材料の前記一部を除去した前記体積内とに、導電性材料を堆積して、前記階段状構造の少なくとも一段の前記導電性部分を形成することと、
を更に含む、請求項21に記載の方法。 - 前記開口部内の前記導電性材料の一部を除去することと、
前記開口部内に別の絶縁性材料を堆積することと、
を更に含む、請求項22に記載の方法。 - 前記階段状構造の少なくとも一つの段の前記導電性部分と、前記別の絶縁性材料の周辺の、前記少なくとも一つの段の隣り合う別の導電性部分との間に、電気接続を形成すること、を更に含む、請求項23に記載の方法。
- 前記導電性構造の前記ランディングをマスクしながら、前記複数の階段状構造のうちの少なくとも一つの階段状構造に対して置換ゲート工程を行うこと、を更に含む、請求項18から請求項24のいずれか1項に記載の方法。
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