JP6427218B2 - 微細凹状フィーチャのSiO2充填及び触媒表面上への選択的SiO2堆積のための方法 - Google Patents
微細凹状フィーチャのSiO2充填及び触媒表面上への選択的SiO2堆積のための方法 Download PDFInfo
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- JP6427218B2 JP6427218B2 JP2017079214A JP2017079214A JP6427218B2 JP 6427218 B2 JP6427218 B2 JP 6427218B2 JP 2017079214 A JP2017079214 A JP 2017079214A JP 2017079214 A JP2017079214 A JP 2017079214A JP 6427218 B2 JP6427218 B2 JP 6427218B2
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- silanol
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- HLDBBQREZCVBMA-UHFFFAOYSA-N hydroxy-tris[(2-methylpropan-2-yl)oxy]silane Chemical compound CC(C)(C)O[Si](O)(OC(C)(C)C)OC(C)(C)C HLDBBQREZCVBMA-UHFFFAOYSA-N 0.000 claims description 3
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- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 1
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- 229910006400 μ-Cl Inorganic materials 0.000 description 1
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Description
本出願は、2016年4月12日に出願された米国仮特許出願第62/321,662号に関連し、これに基づく優先権を主張しており、その全内容は参照により本明細書に組み込まれる。本出願は、2016年5月18日に出願された米国仮特許出願第62/338,189号に関連し、これに基づく優先権を主張しており、その全内容は参照により本明細書に組み込まれる。本出願は、2016年11月22日に出願された米国仮特許出願第62/425,563号に関連し、これに基づく優先権を主張しており、その全内容は参照により本明細書に組み込まれる。
本発明は、基板を処理する方法に関し、より具体的には、基板上の微細な凹状フィーチャ、例えば、浅いトレンチ分離(STI)構造を形成する微細な凹状フィーチャのシリコンダイオキサイド(SiO2)充填方法及び異なる材料上にSiO2膜を選択的に堆積させる方法に関する。
SiO2は、シリコンマイクロ電子デバイスにおける最も一般的な誘電材料である。しかし、その重要性にもかかわらず、微細な凹状フィーチャのSiO2材料による低温でのボイドレス(void-less)かつシームフリー(seamfree)充填が困難であることが判明している。さらに、低い基板温度で異なる材料上にSiO2膜を選択的に堆積させるための新しい方法が必要とされている。
図1は、本発明の一実施形態による基板を処理するためのプロセスフローチャートであり、図2A〜図2Cは、本発明の一実施形態による基板の処理方法を断面図で概略的に示す。
式:AlL1L2L3Dxを有し、
ここでL1、L2、L3は個々のアニオン性配位子であり、Dは中性ドナー配位子であり、xは0,1又は2であることができる。各L1、L2、L3配位子は、アルコキシド、ハロゲン化物、アリールオキシド、アミド、シクロペンタジエニル、アルキル、シリル、アミジナート、β−ジケトナート、ケトイミネート、シラノエート、及びカルボキシレートからなる群から個々に選択される。D配位子は、エーテル、フラン、ピリジン、ピロール、ピロリジン、アミン、クラウンエーテル、グライム及びニトリルの群から選択することができる。
Claims (20)
- 基板処理方法であって、
凹状フィーチャを含む基板を提供するステップと、
前記凹状フィーチャの表面を金属含有触媒層でコーティングするステップと、
いかなる酸化剤及び加水分解剤も存在しない状態で、前記凹状フィーチャ内にコンフォーマルなSiO2膜を堆積させるために、前記基板を約150℃以下の基板温度でシラノールガスを含むプロセスガスに曝露するステップと、
前記凹状フィーチャが、ボイドフリーかつシームレスなSiO2材料で満たされるまで、前記コンフォーマルなSiO2膜の厚さを増加させるために、前記コーティングするステップ及び前記曝露するステップを少なくとも1回繰り返すステップと、
を含み、
前記コーティングするステップと前記曝露するステップとは、複数回実行され、まず、前記凹状フィーチャの底部を除く前記凹状フィーチャの側壁部のみがAl 2 O 3 でコーティングされ、その後コーティングするステップが繰り返されるたびに、前記凹状フィーチャの底部を除く前記側壁部のみがAlMe 3 でコーティングされる、方法。 - 前記シラノールガスが、トリス(tert−ペントキシ)シラノール、トリス(tert−ブトキシ)シラノール及びビス(tert−ブトキシ)(イソプロポキシ)シラノールからなる群から選択される、請求項1に記載の方法。
- 前記金属含有触媒層は、アルミニウム、チタン又はそれらの組み合わせを含む、請求項1に記載の方法。
- 前記金属含有触媒層は、Al、Al2O3、AlN、AlON、Al含有前駆体、Al合金、CuAl、TiAlN、TaAlN、Ti、TiAlC、TiO2、TiON、TiN、Ti含有前駆体、Ti合金、及びこれらの組み合わせからなる群から選択される、請求項3に記載の方法。
- 前記コーティングするステップが、前記基板をAlMe3ガスに曝露するステップを含む、請求項1に記載の方法。
- 基板処理方法であって、
凹状フィーチャを含む基板を提供するステップと、
前記凹状フィーチャの表面を金属含有触媒層でコーティングするステップと、
いかなる酸化剤及び加水分解剤も存在しない状態で、前記凹状フィーチャ内にコンフォーマルなSiO 2 膜を堆積させるために、前記基板を約150℃以下の基板温度でシラノールガスを含むプロセスガスに曝露するステップと、
前記凹状フィーチャが、ボイドフリーかつシームレスなSiO 2 材料で満たされるまで、前記コンフォーマルなSiO 2 膜の厚さを増加させるために、前記コーティングするステップ及び前記曝露するステップを少なくとも1回繰り返すステップと、
を含み、
前記コーティングするステップと前記曝露するステップとは、複数回実行され、まず、前記凹状フィーチャの底部を除く前記凹状フィーチャの側壁部のみにHfO2がコーティングされ、HfO2上にAl2O3がコーティングされ、その後コーティングするステップが繰り返されるたびに、前記凹状フィーチャの底部を除く前記側壁部のみがAlMe3でコーティングされる、方法。 - 前記曝露するステップの間、前記基板温度は約100℃以下である、請求項1又は6に記載の方法。
- 前記プロセスガスは、シラノールガス及び不活性ガスからなる、請求項1又は6に記載の方法。
- SiO2材料で充填された前記凹状フィーチャが、半導体デバイス内で浅いトレンチ分離(STI)構造を形成する、請求項1又は6に記載の方法。
- 平坦化プロセスにおいて凹状フィーチャの上から過剰なSiO2を除去するステップをさらに含む、請求項1又は6記載の方法。
- 前記除去するステップは、化学機械平坦化(CMP)を用いて行われる、請求項10に記載の方法。
- 前記凹状フィーチャの表面を金属含有触媒層でコーティングするステップは、
前記金属含有触媒層を前記凹状フィーチャの前記底部から除去するステップを含む、
請求項1又は6記載の方法。 - 基板処理方法であって、
第1表面を含む第1材料及び第2表面を含む第2材料を含む基板を準備するステップであって、前記第2表面が金属含有触媒層を含ステップと、
いかなる酸化剤及び加水分解剤も存在しない状態で、前記第1表面ではなく前記第2表面にSiO2膜を堆積させるために、前記基板を約150℃以下の基板温度でシラノールガスを含むプロセスガスに曝露するステップと、
を含む、方法。 - 前記シラノールガスが、トリス(tert−ペントキシ)シラノール、トリス(tert−ブトキシ)シラノール、及びビス(tert−ブトキシ)(イソプロポキシ)シラノールからなる群から選択される、請求項13に記載の方法。
- 前記金属含有触媒層は、アルミニウム、チタン、又はそれらの組み合わせを含む、請求項13に記載の方法。
- 前記金属含有触媒層は、Al、Al2O3、AlN、AlON、Al含有前駆体、Al合金、CuAl、TiAlN、TaAlN、Ti、TiAlC、TiO2、TiON、TiN、Ti含有前駆体、Ti合金及びこれらの組み合わせからなる群から選択される、請求項13に記載の方法。
- 前記第1材料は、シリコン、ゲルマニウム、シリコンゲルマニウム、誘電体材料、金属及び金属含有材料からなる群から選択される、請求項13に記載の方法。
- 前記誘電体材料が、SiO2、SiON、SiN、高比誘電率材料、低比誘電率材料及び超低比誘電率材料からなる群から選択される、請求項17に記載の方法。
- 前記曝露中に前記基板温度が約100℃以下である、請求項13に記載の方法。
- 前記プロセスガスは、シラノールガス及び不活性ガスからなる、請求項13に記載の方法。
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US201662321662P | 2016-04-12 | 2016-04-12 | |
US62/321,662 | 2016-04-12 | ||
US201662338189P | 2016-05-18 | 2016-05-18 | |
US62/338,189 | 2016-05-18 | ||
US201662425563P | 2016-11-22 | 2016-11-22 | |
US62/425,563 | 2016-11-22 |
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