TWI806881B - 金屬閘極之低厚度相依功函數nMOS整合 - Google Patents

金屬閘極之低厚度相依功函數nMOS整合 Download PDF

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TWI806881B
TWI806881B TW107124045A TW107124045A TWI806881B TW I806881 B TWI806881 B TW I806881B TW 107124045 A TW107124045 A TW 107124045A TW 107124045 A TW107124045 A TW 107124045A TW I806881 B TWI806881 B TW I806881B
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伯方 馬
沙謝德利 甘古利
陳世忠
拉傑許 薩席亞納拉亞南
艾塔希 巴蘇
董琳
吉田尚美
尚澔 柳
立其 吳
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美商應用材料股份有限公司
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Abstract

膜堆疊及形成膜堆疊之方法，膜堆疊包含在基板上的高介電常數介電層、在高介電常數介電層上的高介電常數覆蓋層、在高介電常數覆蓋層上的n型金屬層及在n型金屬層上的n型金屬覆蓋層。n型金屬層具有與高介電常數覆蓋層相鄰的富含鋁介面。

Description

金屬閘極之低厚度相依功函數nMOS整合
本揭示案之實施例大致上關於半導體製造，包含用於形成n型金屬堆疊之製程。更具體而言，本揭示案之實施例涉及n型金屬閘極堆疊及其生產方法。
MOSFET的連續尺寸縮小(scaling)造成在形成金屬閘極堆疊之後對於低電阻率金屬（例如，鎢）沉積的較小的閘極填充體積。適合的n型金屬膜具有低功函數(work function; WF)厚度相依性及低電阻率。此外，帶邊功函數(band edge work function)效能應實現可用的臨界電壓(threshold voltage)行為並且使短通道效應最小化。
現存n型金屬TiAlC具有高電阻率（＞2000 µΩ-cm）並且需要約30 Å才能實現10 nm元件的有用功函數。將TiAl膜厚度薄化至20 Å及低於20 Å導致有效功函數顯著增加。進一步的功函數降低取決於增加的Al濃度，此舉造成整合(integration)可靠性及腔室缺陷挑戰。
因此，本領域需要整合方案、閘極堆疊及用於功函數縮小的新穎材料。
本揭示案之一或更多個實施例涉及膜堆疊，該膜堆疊包括在基板上的高介電常數介電層。高介電常數覆蓋層在高介電常數介電層上。n型金屬層在高介電常數覆蓋層上。n型金屬層具有與高介電常數覆蓋層相鄰的富含鋁介面，該富含鋁介面在高介電常數覆蓋層與n型金屬覆蓋層之間或在高介電常數覆蓋層與高介電常數介電層之間。n型金屬覆蓋層在n型金屬層上。
本揭示案之附加實施例涉及形成膜堆疊之方法。在基板上形成高介電常數介電層。在高介電常數介電層上形成高介電常數覆蓋層。在高介電常數覆蓋層上形成n型金屬層。n型金屬層具有與高介電常數覆蓋層相鄰的富含鋁介面，該富含鋁介面在高介電常數覆蓋層與n型金屬覆蓋層之間或在高介電常數覆蓋層與高介電常數介電層之間。在n型金屬層上形成n型金屬覆蓋層。
本揭示案之進一步實施例涉及膜堆疊，包括具有表面的基板，該表面包括氧化矽層。HfO2 層在氧化矽層上。HfO2 層具有在約10 Å至約20 Å的範圍中的厚度。氮化鈦層在HfO2 層上。氮化鈦層具有在約5 Å至約20 Å的範圍中的厚度。n型金屬層在氮化鈦層上，該n型金屬層包括TaSiAl且具有在約10 Å至約30 Å的範圍中的厚度。n型金屬層具有與氮化鈦層相鄰的富含鋁介面。n型金屬覆蓋層在n型金屬層上，該n型金屬覆蓋層包括在約10 Å至約60 Å的範圍中的氮化鈦。
在描述本揭示案之若干示例性實施例之前，應理解，本揭示案不限於以下描述中記載的構造或製程步驟之細節。本揭示案能夠具有其他實施例並且能夠以各種方式來實踐或執行。
如本說明書及申請專利範圍所使用的，用語「基板」指表面或表面之一部分，在該表面或表面之一部分上進行製程。本領域熟知技術者亦將理解，除非上下文另有明確說明，否則對基板的參照可僅指基板之一部分。另外，參照在基板上的沉積可意謂裸基板及具有在其上沉積或形成的一或更多個膜或特徵的基板。
本文使用的「基板」指任何基板或在基板上形成的材料表面，在該基板或材料表面上實行處理。例如，取決於應用，可在其上實行處理的基板表面包含但不限於，如矽、氧化矽、應變矽、絕緣體上矽(SOI)、摻雜碳的矽氧化物、氮化矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石的材料，以及任何其他材料，如金屬、金屬氮化物、金屬合金，以及其他導電材料。基板包含但不限於半導體晶圓。可將基板暴露於預處理製程以拋光、蝕刻、還原、氧化、羥基化(hydroxylate)（或以其他方式產生或接枝目標化學官能基以賦予化學官能度）、退火及/或烘烤基板表面。除了直接在基板本身之表面上進行處理之外，在本揭示案中，所揭示的膜處理步驟中之任一者亦可在基板上形成的底層(underlayer)上實行，如以下更詳細地揭示，並且用語「基板表面」欲包含上下文指出的上述底層。因此，例如，在已將膜/層或部分膜/層沉積至基板表面上的情況下，新沉積的膜/層之暴露的表面變成基板表面。給定的基板表面包括的內容將取決於待沉積的材料以及所使用的特定化學物。
本揭示案之實施例有利地提供形成具有低功函數的n型金屬層之方法。一些實施例有利地提供具有小的厚度的低功函數n型金屬層。一些實施例有利地提供用於沉積具有富含鋁介面的n型金屬層的方法。
參照第1A圖，本揭示案之一或更多個實施例涉及膜堆疊10。在一些實施例中，膜堆疊10為金氧半導體(MOS)中的閘極堆疊之一部分。
膜堆疊10形成在基板5上，基板5可具任何適合的材料或形狀。在所繪示的實施例中，基板5為平坦表面，並且膜堆疊10是由矩形框所表示。然而，本領域熟知技術者將理解，基板5可具有一或更多個特徵（即，溝槽或穿孔），並且可將膜堆疊10形成為符合基板5表面之形狀。
在一些實施例中，氧化物層7位於基板5上。氧化物層7可藉由基板5之表面之氧化或在基板上沉積作為膜而形成。氧化物層7可具任何適合的材料，包含但不限於氧化矽。一些實施例之氧化物層7為基板5上的原生氧化物。例如，矽基板可在空氣中氧化以在矽上形成原生氧化物層。在一些實施例中，氧化物層之厚度小於或等於約15 Å、14 Å、13 Å、12 Å、11 Å、10 Å、9 Å、8 Å、7 Å或6 Å。在一些實施例中，氧化物層7的厚度在約2 Å至約15 Å的範圍中，或在約5 Å至約10 Å的範圍中。
在基板5或氧化物層7上形成高介電常數介電層20。氧化物層7為任選的。高介電常數介電層20可為任何適合的高介電常數介電質，包含但不限於二氧化鉿(HfO2 )。在一些實施例中，高介電常數介電層20之厚度在約5Å至約30 Å的範圍中，或在約10 Å至約20 Å的範圍中。在一些實施例中，基板5在形成高介電常數介電層20之前包括氧化物層7。在一些實施例中，氧化物層7為原生氧化物或有意地形成的氧化物層7。在一些實施例中，高介電常數介電層20形成在基板5上，而沒有介於中間的氧化物層7。
高介電常數介電層20可由任何適合的製程來形成。在一些實施例中，高介電常數介電層20是使用鉿前驅物（例如，四（二甲胺基）鉿(tetrakis(dimethylamino)hafnium)）及氧化劑（例如，O2 ）藉由原子層沉積或化學氣相沉積來沉積。
在高介電常數介電層20上形成高介電常數覆蓋層30。高介電常數覆蓋層30可為任何適合的材料，包含但不限於氮化鈦。一些實施例之高介電常數覆蓋層30的厚度在約5 Å至約20 Å的範圍中。
在高介電常數覆蓋層30上形成n型金屬層40。n型金屬層40繪示為兩層：富含鋁層42及塊材n型金屬層44。n型金屬層40經沉積為單一材料，並且介面層（即，富含鋁層42）可經由n型金屬層40中鋁原子之擴散及遷移來形成。
在一些實施例中，n型金屬層40包括鋁/鉭矽化物(Al/TaSi)膜。n型金屬層40（即，Al/TaSi層）可藉由原子層沉積(ALD)來沉積，其經由對鉭(Ta)、鋁(Al)及矽(Si)前驅物交替地進行脈衝(pulsing)而由氬(Ar)（或其他惰性氣體）淨化(purge)來分離。前驅物脈衝之順序可變化。Al/TaSi膜可在任何適合的溫度下沉積。在一些實施例中，Al/TaSi沉積之溫度在約250ºC至約600ºC的範圍中，或在約300ºC至約500ºC的範圍中，或在約400ºC至約450ºC的範圍中。沉積期間的壓力可在約10 mT至約100 T的範圍中，或在約100 mT至約50 T的範圍中，或在約1 mT至約10 T的範圍中，或約3 T。
不受任何特定操作之理論的侷限，據信在沉積期間或在沉積之後，鋁分離(segregate)至介面，從而形成介面富含鋁層42。富含鋁層42中的鋁濃度可在按原子計(atomic basis)約1%至約20%的範圍中。在一些實施例中，富含鋁層42按原子計的鋁濃度在約5%至約18%的範圍中，或在約8%至約15%的範圍中。
塊材n型金屬層44之鋁成分小於富含鋁層42之鋁成分。在一些實施例中，塊材n型金屬層44之鋁濃度大於或等於比富含鋁層42低約0.5原子%、1原子%、1.5原子%、2原子%、2.5原子%、3原子%、3.5原子%、4原子%、4.5原子%或5原子%。在一些實施例中，塊材n型金屬層44之鋁成分按原子計小於或等於約10%、9%、8%、7%、6%、5%、4%、3%、2%或1%。在一些實施例中，塊材n型金屬層44之鋁成分在約2原子%至約5原子%的範圍中。
n型金屬層40之碳含量可受到例如用於沉積膜的前驅物及沉積條件的影響。在一些實施例中，塊材n型金屬層44按原子計具有小於或等於約20%、18%、16%、14%、12%、10%、9%、8%、7%、6%、5%、4%、3%或2%的碳含量。
n型金屬層40具有在約10 Å至約30 Å的範圍中的總厚度。在一些實施例中，n型金屬層40具有小於或等於約20 Å的總厚度。
富含鋁層42可具有小於或等於約10個單層(monolayer)的厚度。在一些實施例中，富含鋁層42的厚度小於約5個單層。在一些實施例中，富含鋁層42的厚度小於或等於約1 nm。據信，薄的富含Al的介面層可顯著地降低功函數。可藉由調整Al原子%來調諧膜功函數。在一些實施例中，功函數小於或等於約4.25 eV、4.2 eV、4.15 eV、4.1 eV、4.05 eV或4eV。
富含鋁層42位於與高介電常數覆蓋層30相鄰處在高介電常數覆蓋層30與塊材n型金屬層44之間。在一些實施例中，富含鋁層42位於與高介電常數覆蓋層30及高介電常數介電層20相鄰處，如第1B圖所繪示。在一些實施例中，富含鋁介面層可在HfO2 /TiN層之介面處或在TiN/TaSi層之介面處。令人驚訝地發現，塊材鉭矽化物膜提供優異的電阻率，並且具有與富含鋁的介面層較小的厚度相依功函數效能。
取決於高介電常數覆蓋層30（例如，TiN）膜厚度，Al可擴散通過高介電常數覆蓋層30並且留駐於高介電常數介電層20與高介電常數覆蓋層30之介面處。Al/TaSi可原位沉積或藉由非原位沉積兩者與TiN層整合在一起。用於Al/TaSi的原位TiN覆蓋可防止表面氧化，表面氧化會人為地增加膜厚度及功函數。
隨著膜之厚度減小，n型金屬層之功函數通常變大。例如，隨著膜之厚度從3 nm減小至2 nm，TiAlC n型金屬層之功函數增加超過0.06 V。令人驚訝地發現，Al/TaSi n型金屬層之功函數具有更低的厚度相依性。在一些實施例中，隨著n型金屬膜之厚度從3 nm減小至2 nm，n型金屬膜之功函數增加了小於或等於約0.05 V。在一些實施例中，隨著n型金屬膜之厚度從3 nm減小至2 nm，功函數增加了小於或等於約0.045 V、0.04 V、0.035 V、0.03 V、0.025 V、0.02 V、0.015 V或0.01 V。
在n型金屬層40上形成n型金屬覆蓋層50。n型金屬覆蓋層50可為任何適合的材料，包含但不限於氮化鈦。一些實施例之n型金屬覆蓋層50的厚度在約10 Å至約60 Å的範圍中，或在約20 Å至約50 Å的範圍中。
在一些實施例中，在n型金屬覆蓋層50上形成金屬層60。金屬層60可為任何適合的金屬，包含但不限於鎢、銅及鈷。在一些實施例中，金屬層60包括鎢。金屬層60可藉由任何適合的技術來形成，包含原子層沉積、化學氣相沉積及物理氣相沉積。
如本文使用的「原子層沉積」或「循環沉積」指包括依序暴露兩種或更多種反應性化合物以在基板表面上沉積材料層的製程。如本說明書及所附申請專利範圍中使用的，用語「反應性化合物」、「反應性氣體」、「反應性物種」、「前驅物」、「製程氣體」等可互換使用以意指具有能夠在表面反應（例如，化學吸附、氧化、還原、環加成反應）中與基板表面或基板表面上的材料反應的物種的物質。基板或基板之一部分依序暴露於兩種或更多種反應性化合物，這些反應性化合物被引入處理腔室之反應區中。
在時域ALD製程中，將每種反應性化合物的暴露分隔一段時間延遲，以允許每種化合物在基板表面上黏附及/或反應，然後從處理腔室清除(purge)。在隨後的暴露之間藉由淨化處理腔室來防止反應性氣體混合。
在空間ALD製程中，反應性氣體流入處理腔室內的不同處理區域中。不同的處理區域自相鄰的處理區域分離，使得反應性氣體不混合。基板可在處理區域之間移動，以將基板個別地暴露於處理氣體。在基板移動期間，基板表面或基板表面上的材料之不同部分暴露於兩種或更多種反應性化合物，使得基板上的任何給定點實質上不同時暴露於多於一種的反應性化合物。如本領域熟知技術者將理解，由於處理腔室內的氣體擴散，有可能一小部分的基板可能同時暴露於多種反應性氣體，並且同時暴露為非故意的，除非另有指出。
在時域ALD製程之一種態樣中，將第一反應性氣體（即，第一前驅物或化合物A）脈衝進入反應區，然後進行第一次時間延遲。將第二種前驅物或化合物B脈衝進入反應區，然後進行第二次時間延遲。在每個時間延遲期間，將淨化氣體（如氬）引入處理腔室以淨化反應區或以其他方式從反應區移除任何殘留的反應性化合物或反應產物或副產物。或者，淨化氣體可在整個沉積製程中連續流動，使得在反應性化合物之脈衝之間的時間延遲期間僅淨化氣體流動。交替地對反應性化合物進行脈衝，直到在基板表面上形成預定的膜或膜厚度。在任何一種情況下，脈衝化合物A、淨化氣體、化合物B及淨化氣體之ALD製程是循環。循環可從化合物A或化合物B開始，並且繼續循環之個別順序，直到達成具有預定厚度的膜。
在空間ALD製程之一種態樣中，第一反應性氣體及第二反應性氣體（例如，氫自由基）同時輸送至反應區，但藉由惰性氣幕及/或真空幕分離。氣幕可為惰性氣體流入處理腔室與真空流流出處理腔室之組合。基板相對於氣體分配設備移動，使得基板上的任何給定點暴露於第一反應性氣體及第二反應性氣體。
如本文使用的「脈衝」或「劑量」指間歇地或非連續地引入處理腔室的一定量的源氣體。每個脈衝內特定化合物的量可隨時間變化，其取決於脈衝之持續時間。特定的製程氣體可包含單一化合物或兩種或更多種化合物之混合物/組合。
每個脈衝/劑量的持續時間為可變的，並且可經調整以適應例如處理腔室之容量以及與該處理腔室耦接的真空系統之能力。此外，製程氣體之劑量時間可根據製程氣體之流速、製程氣體之溫度、控制閥之類型、所採用製程腔室之類型以及製程氣體之成分吸附至基板表面上的能力而變化。劑量時間亦可根據所形成的層之類型及所形成的元件之幾何形狀而變化。劑量時間應足夠長以提供足以吸附/化學吸附至基板之實質上整個表面上並且在該表面上形成製程氣體成分之層的一定體積的化合物。
本揭示案之一些實施例提供在基板上形成保形膜之方法。保形膜可沉積在基板之一些或全部表面上。例如，保形膜可沉積在具有至少一個表面特徵（例如，溝槽或穿孔）的基板上。保形膜在特徵之頂部具有與在特徵之底部相同的厚度。在一些實施例中，膜之保形性經量測為在特徵之頂部的厚度相對於在特徵之底部的厚度，並且大於或等於約90%、91%、92%、93%、94%、95%、96%、97%、98%、99%或約100%。
貫穿本說明書對「一個實施例」、「某些實施例」、「一或更多個實施例」或「實施例」的參照意指結合實施例所述的特定特徵、結構、材料或特性包含於本揭示案之至少一個實施例中。因此，在貫穿本說明書中各處出現的短語如「在一或更多個實施例中」、「在某些實施例中」、「在一個實施例中」或「在實施例中」未必指本揭示案之相同的實施例。此外，特定特徵、結構、材料或特性可在一或更多個實施例中以任何適合的方式來組合。
儘管本文已參照特定實施例描述了本揭示案，但應理解，這些實施例僅為說明本揭示案之原理及應用。對於本領域熟知技術者顯而易見的是，在不脫離本揭示案之精神及範疇下，可對本揭示案之方法及設備作各種修改及變化。因此，預期本揭示案包含在所附申請專利範圍及其均等物之範疇內的修改及變化。
5‧‧‧基板7‧‧‧氧化物層10‧‧‧膜堆疊20‧‧‧高介電常數介電層30‧‧‧高介電常數覆蓋層40‧‧‧n型金屬層42‧‧‧富含鋁層44‧‧‧塊材n型金屬層50‧‧‧n型金屬覆蓋層60‧‧‧金屬層
為了詳細地瞭解本揭示案之上述特徵的方式，可藉由參照實施例來得到以上簡要總結的本揭示案之更特定敘述，該等實施例中之一些實施例繪示於附圖中。然而，應注意，附圖僅繪示本揭示案之典型實施例，且因此不應被視為限制本揭示案之範疇，因為本揭示案可容許其他等效實施例。
第1A圖示出根據本揭示案之一或更多個實施例的膜堆疊；及
第1B圖示出根據本揭示案之一或更多個實施例的膜堆疊。
在附圖中，類似的部件及/或特徵可具有相同的參考標號。此外，相同類型的各種部件可藉由用短劃線跟隨參考標號及區分類似部件的第二標號來區分。若在說明書中僅使用第一參考標號，則該描述適用於具有相同第一參考標號的任何一個類似的部件，而與第二參考標號無關。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
5‧‧‧基板
7‧‧‧氧化物層
10‧‧‧膜堆疊
20‧‧‧高介電常數介電層
30‧‧‧高介電常數覆蓋層
40‧‧‧n型金屬層
42‧‧‧富含鋁層
44‧‧‧塊材n型金屬層
50‧‧‧n型金屬覆蓋層
60‧‧‧金屬層

Claims (18)

  1. 一種膜堆疊，包括：一高介電常數介電層，在一基板上；一高介電常數覆蓋層，在該高介電常數介電層上；一n型金屬層，在該高介電常數覆蓋層上，其中該n型金屬層包括鉭、矽及鋁，及其中該鋁從該n型金屬層遷移經過該高介電常數覆蓋層以形成與該高介電常數覆蓋層相鄰的一富含鋁介面，該富含鋁介面在該高介電常數覆蓋層與該高介電常數介電層之間；及一n型金屬覆蓋層，在該n型金屬層上。
  2. 如請求項1所述之膜堆疊，其中該高介電常數介電層包括HfO2。
  3. 如請求項2所述之膜堆疊，其中該高介電常數介電層具有在約10Å至約20Å的範圍中的一厚度。
  4. 如請求項1所述之膜堆疊，其中該高介電常數覆蓋層包括氮化鈦。
  5. 如請求項4所述之膜堆疊，其中該高介電常數覆蓋層具有在約5Å至約20Å的範圍中的一厚度。
  6. 如請求項1所述之膜堆疊，其中該n型金屬層具有在約10Å至約30Å的範圍中的一厚度。
  7. 如請求項1所述之膜堆疊，其中該n型金屬覆蓋層包括TiN。
  8. 如請求項7所述之膜堆疊，其中該n型金屬覆蓋層具有在約10Å至約60Å的範圍中的一厚度。
  9. 如請求項1所述之膜堆疊，進一步包括在該高介電常數介電層下方的一氧化矽層。
  10. 如請求項9所述之膜堆疊，其中該氧化矽層具有在約5Å至約10Å的範圍中的一厚度。
  11. 如請求項1所述之膜堆疊，進一步包括在該n型金屬覆蓋層上方的一金屬層，該金屬層包括鎢。
  12. 一種形成一膜堆疊之方法，該方法包括以下步驟：在一基板上形成一高介電常數介電層；在該高介電常數介電層上形成一高介電常數覆蓋層；在該高介電常數覆蓋層上形成一n型金屬層，其中該n型金屬層包括鉭、矽及鋁，及其中該鋁從該n型金屬層遷移經過該高介電常數覆蓋層以形成與該高介電常數覆蓋層相鄰的一富含鋁介面，該富含鋁介面在該高介電常數覆蓋層與該高介電常數介電層之間；及在該n型金屬層上形成一n型金屬覆蓋層。
  13. 如請求項12所述之方法，其中該高介電常數介電層包括HfO2且具有在約10Å至約20Å的範圍中的一厚度。
  14. 如請求項12所述之方法，其中該高介電常數覆蓋層包括氮化鈦且具有在約5Å至約20Å的範圍中的一厚度。
  15. 如請求項12所述之方法，其中該n型金屬層具有在約10Å至約30Å的範圍中的一厚度。
  16. 如請求項12所述之方法，其中該n型金屬覆蓋層包括TiN且具有在約10Å至約60Å的範圍中的一厚度。
  17. 如請求項12所述之方法，其中在形成該高介電常數介電層之前該基板包括氧化矽且具有在約5Å至約10Å的範圍中的一厚度，及該方法進一步包括以下步驟：在該n型金屬覆蓋層上方形成一金屬層，該金屬層包括鎢。
  18. 一種膜堆疊，包括：一基板，該基板具有一表面，該表面包括氧化矽層；一HfO2層，在該氧化矽層上，該HfO2層具有在約10Å至約20Å的範圍中的一厚度；氮化鈦層，在該HfO2層上，該氮化鈦層具有在約5Å至約20Å的範圍中的一厚度； 一n型金屬層，在該氮化鈦層上，該n型金屬層包括TaSiAl且具有在約10Å至約30Å的範圍中的一厚度，其中該Al從該n型金屬層遷移經過該氮化鈦層以形成與該氮化鈦層相鄰的一富含鋁介面，該富含鋁介面在該氮化鈦層與該HfO2層之間；及一n型金屬覆蓋層，在該n型金屬層上，該n型金屬覆蓋層包括在約10Å至約60Å的範圍中的氮化鈦。
TW107124045A 2017-07-13 2018-07-12 金屬閘極之低厚度相依功函數nMOS整合 TWI806881B (zh)

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