JP6516797B2 - 周期的処理を使用した選択的膜堆積のための方法及び装置 - Google Patents
周期的処理を使用した選択的膜堆積のための方法及び装置 Download PDFInfo
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- JP6516797B2 JP6516797B2 JP2017134474A JP2017134474A JP6516797B2 JP 6516797 B2 JP6516797 B2 JP 6516797B2 JP 2017134474 A JP2017134474 A JP 2017134474A JP 2017134474 A JP2017134474 A JP 2017134474A JP 6516797 B2 JP6516797 B2 JP 6516797B2
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- metal oxide
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Description
本出願は、2016年7月11日付の米国仮特許出願第62/360,903に関連し、これに基づく優先権を主張するものであり、その全内容は参照により本明細書に組み込まれる。
低比誘電率材料は、小さい空隙(又は孔)を形成するために硬化又は堆積プロセス中の膜の完全な高密度化を妨げるCH3結合を有する酸化ケイ素ベースのマトリックスのような、単相からなる多孔質無機‐有機ハイブリッド膜を含む。なお代替的に、これらの誘電層は、硬化プロセスの間に分解され蒸発する、有機材料の多孔質(例えば粒子の集合体(porogen))を有するカーボンドープシリコン酸化物ベースのマトリックスのような、少なくとも二相からなる多孔質無機‐有機ハイブリッド膜を含むことができる。
化学酸化物層はTMSDMAの過飽和曝露により改質された。「サイクルカウント」とは、ALDプロセス中のハフニウム前駆体及び酸素含有ガスの交互曝露の回数を意味する。図7は、HfO2堆積が改質された化学酸化物層上で妨げられたことを示しており、250℃の基板温度が、より低い180℃の基板温度よりも、選択的堆積により有効であることも示している。
トレース803は、改質された化学酸化物層上にALDにより堆積されたHfO2膜の厚さを示し、表面改質が毎6ALDサイクルの間に(between every 6 ALD cycles)繰り返された。化学酸化物層はTMSDMAの過飽和曝露により改質された。両ALDプロセスと化学酸化物層の改質とは、250℃の基板温度において、実施された。「サイクルカウント」とは、ALDプロセス中のジルコニウム前駆体及び酸素含有ガスの交互曝露の回数を意味する。図8は、改質された化学酸化物層上へのHfO2堆積が妨げられ、6ALDサイクルごとに表面改質を繰り返すことで、HfO2堆積がさらに妨げられたことを示している。
繰り返し表面改質は、疎水性第1表面から失われた疎水性官能基を、飽和曝露後の脱離によって、補充すると考えられる。
例えば、プロセスチャンバ1の処理は、6ALDサイクル毎に繰り返すことができる。
プロセッシングシステムは、基板をプロセッシングシステム内に及び外に移送するためのゲート弁をさらに含む。
Claims (15)
- 基板上へ選択的に膜を堆積させる方法であって、
第1表面を有する第1材料及び第2表面を有する第2材料を含む基板を提供するステップであって、前記第1材料は誘電材料を含み、前記第2材料は半導体材料又は金属酸化物を除く金属含有材料を含む、提供ステップと、
前記第1表面を、疎水性第1表面を形成するための疎水性官能基を含む反応ガスと反応させる、反応ステップと、
気相堆積によって、前記第2表面上に金属酸化物膜を堆積させるとともに、前記疎水性第1表面上に追加金属酸化物膜を堆積させるステップであって、前記疎水性第1表面上では前記金属酸化物膜の堆積が妨げられ、前記追加金属酸化物膜の厚さは前記金属酸化物膜の厚さより小さい、堆積ステップと、
前記追加金属酸化物膜を前記疎水性第1表面から除去することにより、前記金属酸化物膜が前記疎水性第1表面上でなく前記第2表面上に選択的に形成される、除去ステップと、
を含む、方法。 - 前記反応ステップ及び前記堆積ステップを少なくとも1回繰り返すステップ、
をさらに含む、請求項1記載の方法。 - 前記除去するステップは、原子層エッチング(ALE)プロセスを含む、
請求項1記載の方法。 - 前記除去ステップに続いて、前記反応ステップ、前記堆積ステップ及び前記除去ステップを少なくとも1回繰り返すステップ、
をさらに含む、請求項1記載の方法。 - 前記第1表面及び前記第2表面は、少なくとも同じ平面にある水平面である、
請求項1記載の方法。 - 前記第1表面は、前記第1材料の水平面及び前記第1材料内に形成された凹状フィーチャの垂直面を含み、
前記第2表面は、前記凹状フィーチャ内で前記金属含有材料の表面を含む、
請求項1乃至4いずれか1項記載の方法。 - 前記第1表面はヒドロキシ末端であり、前記疎水性第1表面はメチル末端である、
請求項1記載の方法。 - 前記金属含有材料は、金属、金属窒化物及びそれらの化合物からなるグループから選択される、
請求項1記載の方法。 - 前記金属含有材料は、W、Cu、Co、Ru、TiN、TaN、TaSiN、TiSiN、CoSi及びそれらの化合物からなるグループから選択され、
前記半導体材料は、Si、Ge及びそれらの化合物からなるグループから選択される、
請求項1記載の方法。 - 前記金属酸化物膜は、HfO2、ZrO2、TiO2、Al2O3及びそれらの化合物からなるグループから選択されることができる、
請求項1記載の方法。 - 前記誘電材料は、SiO2、SiN、SiON、低比誘電率材料、高比誘電率材料及びそれらの化合物からなるグループから選択される、
請求項1記載の方法。 - 前記反応ガスは、シリコン含有ガスを含む、
請求項1記載の方法。 - 前記シリコン含有ガスは、アルキルシラン、アルコキシシラン、アルキルアルコキシシラン、アルキルシロキサン、アルコキシシロキサン、アルキルアルコキシシロキサン、アリールシラン、アシルシラン、アリールシロキサン、アシルシロキサン、シラザン及びそれらの化合物からなるグループから選択される、
請求項12記載の方法。 - 前記反応ガスは、ジメチルシリルジメチルアミン(DMSDMA)、トリメチルシリルジメチルアミン(TMSDMA)、ビス(ジメチルアミノ)ジメチルシラン(BDMADMS)、N,O−ビストリメチルシリルトリフルオロアセトアミド(BSTFA)、トリメチルシリル−ピロール(TMS−ピロール)及びそれらの化合物からなるグループから選択される、
請求項1記載の方法。 - 前記反応するステップの前に、前記第2表面が実質的に酸素フリーにするために、前記第2表面から酸化物層を除去するステップ、
をさらに含む、請求項1記載の方法。
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