JP5957840B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP5957840B2
JP5957840B2 JP2011219843A JP2011219843A JP5957840B2 JP 5957840 B2 JP5957840 B2 JP 5957840B2 JP 2011219843 A JP2011219843 A JP 2011219843A JP 2011219843 A JP2011219843 A JP 2011219843A JP 5957840 B2 JP5957840 B2 JP 5957840B2
Authority
JP
Japan
Prior art keywords
diameter
etching
wiring
resist pattern
small
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2011219843A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013080813A5 (enExample
JP2013080813A (ja
Inventor
正永 深沢
正永 深沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2011219843A priority Critical patent/JP5957840B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Priority to US13/617,806 priority patent/US8871633B2/en
Priority to CN201810824927.5A priority patent/CN109273430B/zh
Priority to CN201210375078.2A priority patent/CN103035615B/zh
Priority to CN201910146438.3A priority patent/CN110060956B/zh
Publication of JP2013080813A publication Critical patent/JP2013080813A/ja
Priority to US14/494,134 priority patent/US9293411B2/en
Publication of JP2013080813A5 publication Critical patent/JP2013080813A5/ja
Priority to US14/831,640 priority patent/US9425142B2/en
Priority to US15/193,875 priority patent/US9627359B2/en
Application granted granted Critical
Publication of JP5957840B2 publication Critical patent/JP5957840B2/ja
Priority to US15/474,417 priority patent/US9859214B2/en
Priority to US15/815,023 priority patent/US10157837B2/en
Priority to US16/188,581 priority patent/US10504839B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011219843A 2011-10-04 2011-10-04 半導体装置の製造方法 Expired - Fee Related JP5957840B2 (ja)

Priority Applications (11)

Application Number Priority Date Filing Date Title
JP2011219843A JP5957840B2 (ja) 2011-10-04 2011-10-04 半導体装置の製造方法
US13/617,806 US8871633B2 (en) 2011-10-04 2012-09-14 Semiconductor device and manufacturing method of the same
CN201810824927.5A CN109273430B (zh) 2011-10-04 2012-09-27 半导体装置及其制造方法
CN201210375078.2A CN103035615B (zh) 2011-10-04 2012-09-27 半导体装置及其制造方法
CN201910146438.3A CN110060956B (zh) 2011-10-04 2012-09-27 半导体装置的制造方法
US14/494,134 US9293411B2 (en) 2011-10-04 2014-09-23 Semiconductor device and manufacturing method of the same
US14/831,640 US9425142B2 (en) 2011-10-04 2015-08-20 Semiconductor device and manufacturing method of the same
US15/193,875 US9627359B2 (en) 2011-10-04 2016-06-27 Semiconductor device and manufacturing method of the same
US15/474,417 US9859214B2 (en) 2011-10-04 2017-03-30 Semiconductor device and manufacturing method of the same
US15/815,023 US10157837B2 (en) 2011-10-04 2017-11-16 Semiconductor device and manufacturing method of the same
US16/188,581 US10504839B2 (en) 2011-10-04 2018-11-13 Semiconductor device and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011219843A JP5957840B2 (ja) 2011-10-04 2011-10-04 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2013080813A JP2013080813A (ja) 2013-05-02
JP2013080813A5 JP2013080813A5 (enExample) 2014-11-13
JP5957840B2 true JP5957840B2 (ja) 2016-07-27

Family

ID=47991806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011219843A Expired - Fee Related JP5957840B2 (ja) 2011-10-04 2011-10-04 半導体装置の製造方法

Country Status (3)

Country Link
US (7) US8871633B2 (enExample)
JP (1) JP5957840B2 (enExample)
CN (3) CN109273430B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5957840B2 (ja) * 2011-10-04 2016-07-27 ソニー株式会社 半導体装置の製造方法
CN103915462B (zh) * 2014-04-04 2016-11-23 豪威科技(上海)有限公司 半导体器件制备方法以及堆栈式芯片的制备方法
CN104979329B (zh) * 2014-04-10 2018-08-10 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
KR102387948B1 (ko) 2015-08-06 2022-04-18 삼성전자주식회사 Tsv 구조물을 구비한 집적회로 소자
CN108598097A (zh) * 2018-01-09 2018-09-28 德淮半导体有限公司 形成穿通硅通孔结构的方法及形成图像传感器的方法
US11069526B2 (en) * 2018-06-27 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Using a self-assembly layer to facilitate selective formation of an etching stop layer
CN110858597B (zh) * 2018-08-22 2022-03-11 中芯国际集成电路制造（天津）有限公司 硅通孔结构的形成方法、cis晶圆的形成方法及cis晶圆
CN109148361B (zh) 2018-08-28 2019-08-23 武汉新芯集成电路制造有限公司 半导体器件及其制作方法
CN109449091B (zh) * 2018-11-05 2020-04-10 武汉新芯集成电路制造有限公司 半导体器件的制作方法
CN111261603B (zh) * 2018-11-30 2025-04-25 长鑫存储技术有限公司 用于半导体结构的互连方法与半导体结构
KR102646012B1 (ko) * 2019-02-18 2024-03-13 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11600519B2 (en) * 2019-09-16 2023-03-07 International Business Machines Corporation Skip-via proximity interconnect
KR20230002752A (ko) * 2020-04-17 2023-01-05 후아웨이 테크놀러지 컴퍼니 리미티드 반도체 구조물 및 그 제조 방법
EP4002437B1 (en) 2020-09-22 2023-08-02 Changxin Memory Technologies, Inc. Method of forming a contact window structure
CN114256417A (zh) 2020-09-22 2022-03-29 长鑫存储技术有限公司 电容结构及其形成方法
US11929280B2 (en) 2020-09-22 2024-03-12 Changxin Memory Technologies, Inc. Contact window structure and method for forming contact window structure
CN114256134A (zh) * 2020-09-22 2022-03-29 长鑫存储技术有限公司 接触窗结构及其形成方法
CN114256135A (zh) 2020-09-22 2022-03-29 长鑫存储技术有限公司 开口结构及其形成方法、接触插塞及其形成方法
CN114171394B (zh) * 2021-06-18 2025-04-11 李勇 半导体装置的制备方法和半导体装置
CN113764337B (zh) * 2021-11-09 2022-02-22 绍兴中芯集成电路制造股份有限公司 导电插塞的制造方法及半导体结构

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19516487C1 (de) * 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Verfahren zur vertikalen Integration mikroelektronischer Systeme
JPH09199586A (ja) 1996-01-12 1997-07-31 Sony Corp 半導体装置の製造方法
US5824579A (en) * 1996-04-15 1998-10-20 Motorola, Inc. Method of forming shared contact structure
JPH11340322A (ja) * 1998-05-21 1999-12-10 Sony Corp 半導体装置およびその製造方法
JP2001135724A (ja) * 1999-11-10 2001-05-18 Mitsubishi Electric Corp 半導体装置の製造方法
JP3400770B2 (ja) * 1999-11-16 2003-04-28 松下電器産業株式会社 エッチング方法、半導体装置及びその製造方法
JP2001319928A (ja) * 2000-05-08 2001-11-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2001345305A (ja) * 2000-06-01 2001-12-14 Murata Mfg Co Ltd 半導体基板のエッチング方法
JP4778660B2 (ja) * 2001-11-27 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2003179132A (ja) * 2001-12-10 2003-06-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3944838B2 (ja) * 2002-05-08 2007-07-18 富士通株式会社 半導体装置及びその製造方法
JP2003332420A (ja) * 2002-05-10 2003-11-21 Sony Corp 半導体装置の製造方法
JP4193438B2 (ja) * 2002-07-30 2008-12-10 ソニー株式会社 半導体装置の製造方法
JP2004079901A (ja) * 2002-08-21 2004-03-11 Nec Electronics Corp 半導体装置及びその製造方法
US20040099961A1 (en) * 2002-11-25 2004-05-27 Chih-Liang Chu Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same
US7453150B1 (en) * 2004-04-01 2008-11-18 Rensselaer Polytechnic Institute Three-dimensional face-to-face integration assembly
JP4376715B2 (ja) * 2004-07-16 2009-12-02 三洋電機株式会社 半導体装置の製造方法
US20070105362A1 (en) * 2005-11-09 2007-05-10 Kim Jae H Methods of forming contact structures in low-k materials using dual damascene processes
JP4918778B2 (ja) * 2005-11-16 2012-04-18 株式会社日立製作所 半導体集積回路装置の製造方法
JP2007214538A (ja) * 2006-01-11 2007-08-23 Renesas Technology Corp 半導体装置およびその製造方法
JP2007305960A (ja) * 2006-04-14 2007-11-22 Sharp Corp 半導体装置およびその製造方法
JP2008130615A (ja) * 2006-11-16 2008-06-05 Toshiba Corp 半導体記憶装置及びその製造方法
US7994639B2 (en) * 2007-07-31 2011-08-09 International Business Machines Corporation Microelectronic structure including dual damascene structure and high contrast alignment mark
US7704869B2 (en) * 2007-09-11 2010-04-27 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US7897502B2 (en) * 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
JP2010080897A (ja) * 2008-09-29 2010-04-08 Panasonic Corp 半導体装置及びその製造方法
JP5985136B2 (ja) * 2009-03-19 2016-09-06 ソニー株式会社 半導体装置とその製造方法、及び電子機器
JP2010263130A (ja) * 2009-05-08 2010-11-18 Olympus Corp 半導体装置および半導体装置の製造方法
TWI402941B (zh) * 2009-12-03 2013-07-21 Advanced Semiconductor Eng 半導體結構及其製造方法
US8415238B2 (en) * 2010-01-14 2013-04-09 International Business Machines Corporation Three dimensional integration and methods of through silicon via creation
US8399180B2 (en) * 2010-01-14 2013-03-19 International Business Machines Corporation Three dimensional integration with through silicon vias having multiple diameters
JP5440221B2 (ja) * 2010-02-02 2014-03-12 日本電気株式会社 半導体装置の積層構造体の製造方法
JP2011192744A (ja) * 2010-03-12 2011-09-29 Panasonic Corp 半導体装置及びその製造方法
JP4566283B2 (ja) * 2010-03-18 2010-10-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5957840B2 (ja) * 2011-10-04 2016-07-27 ソニー株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US8871633B2 (en) 2014-10-28
CN103035615A (zh) 2013-04-10
US9293411B2 (en) 2016-03-22
US10157837B2 (en) 2018-12-18
US9425142B2 (en) 2016-08-23
US9627359B2 (en) 2017-04-18
US20190080997A1 (en) 2019-03-14
US20170207163A1 (en) 2017-07-20
CN109273430A (zh) 2019-01-25
CN110060956A (zh) 2019-07-26
US20150357313A1 (en) 2015-12-10
CN103035615B (zh) 2020-07-21
CN110060956B (zh) 2022-11-18
US10504839B2 (en) 2019-12-10
US20150008591A1 (en) 2015-01-08
US9859214B2 (en) 2018-01-02
CN109273430B (zh) 2023-01-17
US20130082401A1 (en) 2013-04-04
US20160307877A1 (en) 2016-10-20
JP2013080813A (ja) 2013-05-02
US20180076126A1 (en) 2018-03-15

Similar Documents

Publication Publication Date Title
JP5957840B2 (ja) 半導体装置の製造方法
US20100244199A1 (en) Semiconductor device and method for manufacturing semiconductor device
TWI684242B (zh) 半導體裝置之製造方法及半導體裝置
JP3981026B2 (ja) 多層配線層を有する半導体装置およびその製造方法
CN114078954A (zh) 存储器结构及其形成方法
CN101378035B (zh) 半导体装置的制造方法
TWI871516B (zh) 一種去除在閘極結構上方的階梯高度的方法
TWI713783B (zh) 製作半導體裝置的方法
CN110707068B (zh) 半导体互连结构及其制备方法
JP2006287211A (ja) 半導体装置、積層半導体装置およびそれらの製造方法
JP2008085173A (ja) 半導体装置及びその製造方法
JPH0198243A (ja) 半導体装置の製造方法
JPH0969561A (ja) 半導体装置の製造方法
JP2009054879A (ja) 集積回路の製造方法
TWI701793B (zh) 電子元件及其製造方法
JP2008205366A (ja) 半導体装置の製造方法及び半導体装置
JP2007027234A (ja) 半導体装置及びその製造方法
JP2016213386A (ja) 半導体装置および半導体装置の製造方法
JP2009033209A (ja) 半導体装置及びその製造方法
JP2004253572A (ja) 半導体装置及びその製造方法
JP2007123509A (ja) 半導体装置およびその製造方法
JPH113871A (ja) 半導体装置及びその製造方法
JP2015192011A (ja) 半導体装置及びその製造方法
JP2005142421A (ja) 半導体装置及びその製造方法
JP2006013140A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140929

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140929

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150709

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150714

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150825

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160308

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160509

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160524

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160606

R151 Written notification of patent or utility model registration

Ref document number: 5957840

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees