JP5911068B2 - ワークピース上の誘電体層から材料を除去する方法および装置、並びに、ワークピース上の誘電体層から材料を除去する段階を備える集積回路を製造する方法 - Google Patents
ワークピース上の誘電体層から材料を除去する方法および装置、並びに、ワークピース上の誘電体層から材料を除去する段階を備える集積回路を製造する方法 Download PDFInfo
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- JP5911068B2 JP5911068B2 JP2012543254A JP2012543254A JP5911068B2 JP 5911068 B2 JP5911068 B2 JP 5911068B2 JP 2012543254 A JP2012543254 A JP 2012543254A JP 2012543254 A JP2012543254 A JP 2012543254A JP 5911068 B2 JP5911068 B2 JP 5911068B2
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- plasma
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- temperature
- photoresist
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/08—Planarisation of organic insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
- H10P14/6512—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour
- H10P14/6514—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour by exposure to a plasma
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H10P70/12—Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
- H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- General Physics & Mathematics (AREA)
- Drying Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/636,601 US8591661B2 (en) | 2009-12-11 | 2009-12-11 | Low damage photoresist strip method for low-K dielectrics |
| US12/636,601 | 2009-12-11 | ||
| PCT/US2010/059517 WO2011072042A2 (en) | 2009-12-11 | 2010-12-08 | Low damage photoresist strip method for low-k dielectrics |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013513948A JP2013513948A (ja) | 2013-04-22 |
| JP2013513948A5 JP2013513948A5 (https=) | 2014-01-30 |
| JP5911068B2 true JP5911068B2 (ja) | 2016-04-27 |
Family
ID=44141528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012543254A Expired - Fee Related JP5911068B2 (ja) | 2009-12-11 | 2010-12-08 | ワークピース上の誘電体層から材料を除去する方法および装置、並びに、ワークピース上の誘電体層から材料を除去する段階を備える集積回路を製造する方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US8591661B2 (https=) |
| JP (1) | JP5911068B2 (https=) |
| KR (1) | KR101908737B1 (https=) |
| CN (1) | CN102792423B (https=) |
| SG (1) | SG181165A1 (https=) |
| TW (1) | TWI562225B (https=) |
| WO (1) | WO2011072042A2 (https=) |
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-
2009
- 2009-12-11 US US12/636,601 patent/US8591661B2/en not_active Expired - Fee Related
-
2010
- 2010-12-08 KR KR1020127015129A patent/KR101908737B1/ko not_active Expired - Fee Related
- 2010-12-08 SG SG2012040929A patent/SG181165A1/en unknown
- 2010-12-08 JP JP2012543254A patent/JP5911068B2/ja not_active Expired - Fee Related
- 2010-12-08 WO PCT/US2010/059517 patent/WO2011072042A2/en not_active Ceased
- 2010-12-08 CN CN201080056102.5A patent/CN102792423B/zh not_active Expired - Fee Related
- 2010-12-10 TW TW099143368A patent/TWI562225B/zh not_active IP Right Cessation
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201137970A (en) | 2011-11-01 |
| SG181165A1 (en) | 2012-07-30 |
| WO2011072042A2 (en) | 2011-06-16 |
| CN102792423A (zh) | 2012-11-21 |
| US20140120733A1 (en) | 2014-05-01 |
| KR101908737B1 (ko) | 2018-10-16 |
| KR20120098777A (ko) | 2012-09-05 |
| US20110139176A1 (en) | 2011-06-16 |
| US8591661B2 (en) | 2013-11-26 |
| CN102792423B (zh) | 2016-06-22 |
| TWI562225B (en) | 2016-12-11 |
| WO2011072042A3 (en) | 2011-09-09 |
| JP2013513948A (ja) | 2013-04-22 |
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