JP5911068B2 - Method and apparatus for removing material from a dielectric layer on a workpiece and method for manufacturing an integrated circuit comprising removing material from a dielectric layer on a workpiece - Google Patents

Method and apparatus for removing material from a dielectric layer on a workpiece and method for manufacturing an integrated circuit comprising removing material from a dielectric layer on a workpiece Download PDF

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JP5911068B2
JP5911068B2 JP2012543254A JP2012543254A JP5911068B2 JP 5911068 B2 JP5911068 B2 JP 5911068B2 JP 2012543254 A JP2012543254 A JP 2012543254A JP 2012543254 A JP2012543254 A JP 2012543254A JP 5911068 B2 JP5911068 B2 JP 5911068B2
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plasma
workpiece
method
fluorine
temperature
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JP2013513948A (en
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チャン、デーヴィッド
リー、テッド
グーア、アニルバン
オストロウスキ、キルク
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ノベラス・システムズ・インコーポレーテッドNovellus Systems Incorporated
ノベラス・システムズ・インコーポレーテッドNovellus Systems Incorporated
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Priority to US12/636,601 priority Critical patent/US8591661B2/en
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Priority to PCT/US2010/059517 priority patent/WO2011072042A2/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/31058After-treatment of organic layers
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/42Stripping or agents therefor
    • G03F7/427Stripping or agents therefor using plasma means only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process

Description

  The present invention relates to a method of stripping a photoresist material to remove etch-related residues from the surface of an integrated circuit being fabricated in preparation for further processing.

[Related applications]
This application claims priority based on US patent application Ser. No. 12 / 636,601 (filing date: December 11, 2009). This application is incorporated herein by reference.

  Since the damascene process requires fewer processing steps and has a higher yield than other methods, it is often used as a preferred method in many advanced integrated circuit manufacturing methods. In a damascene process, a metal conductor is formed on an integrated circuit by forming metal lines in an inlaid manner in trenches and vias in a dielectric layer (intermetal dielectric). As part of the damascene process, a photoresist layer is deposited on the dielectric layer. The photoresist is a photosensitive organic polymer that is “spun” in liquid form and dried to form a solid film. The photosensitive photoresist is then exposed through a mask and patterned using a wet solvent. Thereafter, by using a plasma etching process (dry etching), the exposed portion of the dielectric is etched, the pattern is transferred to the dielectric, and a via and a trench are formed in the dielectric layer.

  When the etching of the dielectric layer is complete, the photoresist must be stripped. And, if present, all residues generated in connection with etching must be removed prior to performing subsequent processing to avoid burying impurities in the device. A conventional process for stripping a photoresist uses a plasma formed from a mixed gas obtained by mixing a plurality of gases. The plasma contains oxygen. The highly reactive oxygen-based plasma reacts with the organic photoresist to oxidize the organic photoresist and form a volatile component that is removed from the wafer surface.

  In general, highly oxidizing conditions are also unsuitable for use with low dielectric constant (low-k) materials. Low-k materials are utilized in many modern devices as intermetal dielectrics and / or interlayer dielectrics between conductive interconnects to suppress signal propagation delays due to capacitive effects. The lower the dielectric constant of the dielectric material, the smaller the dielectric capacitance and the smaller the RC delay of the integrated circuit. A low-k dielectric is typically a material based on silicon oxide and contains a certain amount of carbon. Usually called carbon doped oxide (CDO). Although not necessarily proven, it is believed that oxygen collects or removes carbon from low-k materials. In many materials such as CDO, the presence of carbon is useful in lowering the dielectric constant. Thus, as long as oxygen removes carbon from these materials, the dielectric constant will increase. While the process used to manufacture integrated circuits tends to further miniaturization and the dielectric constant of the dielectric material used requires further reduction, the conventional stripping plasma conditions may not be appropriate. I understood.

  For this reason, there is a need to improve the efficiency of stripping photoresist and etch-related materials from dielectric materials, particularly low-k dielectric materials.

  The present invention addresses the above needs by improving the method of stripping photoresist from dielectric material to remove etch-related residues. In one aspect of the invention, a material is removed from a dielectric layer using a hydrogen-based etching process employing a weak oxidant and a fluorine-containing compound. The substrate temperature is maintained at a level below about 160 degrees Celsius, for example, below about 90 degrees Celsius.

  According to certain embodiments, the method includes introducing a gas comprising a weak oxidant, a fluorine-containing compound, and hydrogen into the reaction chamber, applying RF power to form a plasma in the reaction chamber, and At least a portion of the material is changed to a gaseous state to remove at least a portion of the material from the integrated circuit being manufactured. As described above, the method may be used to remove residues generated in the photoresist and / or etching process. The method may be implemented with damascene devices such as single damascene devices and dual damascene devices.

  According to various embodiments, the weak oxidant includes at least one of carbon dioxide, carbon monoxide, nitrous oxide, nitric oxide, nitrogen dioxide, and water. According to certain embodiments, the weak oxidant comprises carbon dioxide. According to certain embodiments, the gas comprises from about 0.1% to about 10.0% carbon dioxide by volume. According to some embodiments, the gas further comprises at least one inert carrier gas, such as helium, argon or nitrogen. According to a particular embodiment, the gas does not contain oxygen molecules.

According to various embodiments, the fluorine-containing compound is nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), hexafluoroethane (C 2 F 6 ), tetrafluoromethane (CF 4 ), trifluoromethane. (CHF 3 ), difluoromethane (CH 2 F 2 ), octofluoropropane (C 3 F 8 ), octofluorocyclobutane (C 4 F 8 ), octofluoro [1-] butane (C 4 F 8 ), octofluoro [2-] Butane (C 4 F 8 ), octofluoroisobutylene (C 4 F 8 ), fluorine (F 2 ) and the like are included. According to certain embodiments, the weak oxidant comprises nitrogen trifluoride. According to certain embodiments, the gas comprises about 5 ppm to about 10% nitrogen trifluoride by volume.

  The method according to the invention can be performed on wafers of any size. Most modern wafer manufacturing facilities use 200 mm or 300 mm wafers. Processing conditions may be determined according to the wafer size. If a 300 mm wafer is utilized, the total gas flow range may be between about 1,000 sccm and about 40,000 sccm. When carbon dioxide is used as the weak oxidant, the range of carbon dioxide flow may be between about 10 sccm and about 2000 sccm, for example, 800 sccm. When nitrogen trifluoride is used as the fluorine-containing gas, the nitrogen trifluoride flow rate range may be between about 1 sccm and 20 sccm, for example, 5 sccm. For a 300 mm wafer, the range of RF plasma power for the plasma is typically between about 300 watts and about 3 kilowatts. The method may be implemented with direct plasma or remote plasma.

  The temperature range of the substrate while the plasma is being applied to the surface of the workpiece is between about 50 degrees Celsius and about 160 degrees Celsius. According to certain embodiments, the temperature of the workpiece is maintained at about 90 degrees Celsius or less. The range of the chamber pressure is, for example, between about 300 mTorr and about 2 Torr. According to some embodiments, the wafer is held at a given bias.

  As described above, the method according to the present invention may be utilized with low-k dielectric materials including carbon-doped low-k dielectric materials such as carbon-doped oxide (CDO). The method according to the invention can be carried out on non-porous and porous dielectric materials such as CDO and other compositions.

  The method according to the invention may be carried out in any suitable reaction chamber. The reaction chamber may be one chamber in an apparatus including a plurality of chambers or may be part of an apparatus including a single chamber. According to some embodiments, a multi-stage removal process is utilized and the fluorine-containing compound is utilized only in some of these stages. According to certain embodiments, the fluorine-containing compound is utilized only in a first group of stages, eg, the first stage. According to embodiments that utilize a multi-station apparatus, the fluorine-containing compound may be utilized as part of a process gas that is used, for example, to generate a plasma at the first station.

  These and other features and advantages of the present invention will be described in more detail below with reference to the accompanying drawings.

FIG. 5 is a process flow diagram illustrating aspects of some embodiments of the present invention utilized to strip photoresist from an integrated circuit during fabrication and remove residues associated with etching.

FIG. 4 is a cross-sectional view of a low-k damascene device during a dry etching process and a photoresist stripping process according to the present invention. FIG. 4 is a cross-sectional view of a low-k damascene device during a dry etching process and a photoresist stripping process according to the present invention. FIG. 4 is a cross-sectional view of a low-k damascene device during a dry etching process and a photoresist stripping process according to the present invention.

FIG. 6 is a cross-sectional view of a low-k device during drying after a photoresist stripping process and an HF testing process according to the present invention. FIG. 6 is a cross-sectional view of a low-k device during drying after a photoresist stripping process and an HF testing process according to the present invention.

1 is a schematic diagram illustrating an apparatus suitable for practicing the present invention.

FIG. 3 is a simplified block diagram illustrating a multi-station stripping tool suitable for practicing the present invention.

<Introduction>
In the following detailed description of the invention, numerous specific embodiments are set forth in order to provide a thorough understanding of the present invention. However, as will be apparent to those skilled in the art, the present invention may be practiced without employing specific and detailed content as described below, utilizing other components or processes. Can also be implemented. In other instances, well known processes, procedures, and components have not been described in detail in order not to unnecessarily obscure aspects of the present invention.

  In this application, the terms “semiconductor wafer”, “wafer”, and “integrated integrated circuit” are used to have the same meaning. Those skilled in the art should understand that the term “in-process integrated circuit” means a silicon wafer during any of the many stages of the integrated circuit manufacturing process. The detailed description set forth below assumes that the present invention is implemented on a wafer. However, the present invention is not limited to this. The workpiece may be of various shapes, sizes and materials. In addition to semiconductor wafers, other workpieces that can utilize the present invention include various articles such as printed wiring boards.

  As described above, the method according to the present invention may be used to efficiently and effectively remove photoresist and etch related materials from low-k dielectric materials. The method according to the invention is not limited to low-k dielectrics. The method is not limited to any particular category of low-k dielectric. For example, the methods described herein include dielectrics with a k value less than 4.0, dielectrics with a k value less than about 2.8, dielectrics with a k value less than about 2.0, “super low-k”. "Or ULK dielectric) may be effective. The low-k dielectric may be porous or non-porous (sometimes referred to as a “dense” low-k dielectric). In general, a high density low-k dielectric has a k value of 2.8 or less, and a porous low-k dielectric has a k value of 2.2 or less. Any suitable composition of low-k dielectric may be utilized. For example, a dielectric based on silicon oxide and doped with fluorine and / or carbon may be used. A dielectric that is not based on silicon oxide, such as a polymer material, may be used. Any suitable process may be utilized when depositing a low-k dielectric. For example, a spin-on film formation method and a CVD film formation method may be used. Any suitable method may be utilized when forming the porous dielectric. In a normal method, a silicon-based backbone and an organic porogen are simultaneously formed, then the porogen component is removed, and the remaining one becomes a porous dielectric film. Another method is the sol-gel method. Specific examples of suitable low-k films include carbon-based films formed by spin-on methods, such as porous films formed by CVD such as SILK (trademark) and Coral (trademark). .

  The method according to the present invention utilizes hydrogen and a weak oxidant and, in certain processes, a plasma generated from a gas containing a fluorine-containing compound. One skilled in the art will understand that the actual species present in the plasma is a mixture of a plurality of different ions and molecules derived from hydrogen, weak oxidants and / or fluorine-containing compounds. It should be noted that other species may also be present in the reaction chamber as the plasma reacts with the organic photoresist and other residues to decompose the organic photoresist and other residues. For example, consider that small amounts of hydrocarbons, carbon dioxide, water vapor and other volatile components are present. One skilled in the art will recognize that the reference to the first one or more gases introduced into the plasma is different from the other one or more gases present after the plasma is formed.

  FIG. 1 is a flowchart illustrating a general high-level process flow according to some embodiments of the present invention. FIG. 1 also illustrates some general processes related to the method according to the present invention in an integrated circuit (IC) manufacturing process, and explains when to use the present invention. To visually illustrate some embodiments of the present invention, FIGS. 2A-2C show cross-sectional views of some of the low-k damascene devices during various related manufacturing processes.

  Referring to FIG. 1, a wafer having a region where a low-k dielectric layer is exposed is etched to form a patterned photoresist layer (block 101). 2A and 2B are diagrams illustrating the formation of a patterned low-k dielectric in the processing of the damascene device 200. FIG. 2A and 2B show the device 200 before and after the dry etching process, respectively. FIG. 2B corresponds to the device state obtained in block 101 of FIG.

  Referring to FIG. 2A, a low-k dielectric layer 203 is deposited on the layer 201. A part of the photoresist 205 is formed on the low-k dielectric layer 203. Depending on the integration scheme, the base layer 201 may be a metal layer such as copper, an etch stop layer such as silicon carbide or silicon nitride, or other types of layers. Photoresist 205 has already been patterned using UV light lithography (or other suitable process), exposing a portion of low-k dielectric layer 203. Device 200 is then subjected to a dry etching process, typically one of sputtering etching, plasma etching, or reactive ion etching.

  As shown in FIG. 2B, the device 200 obtained after the dry etching process has features 210 etched into the ultra-low-k dielectric layer 203. Photoresist portion 205 must be stripped before further processing of the wafer. Note that a “skin” 207 is formed on the upper and side portions of the exposed photoresist portion 205. The skin 207 is a relatively hard photoresist portion that is formed as a result of some dry etching process and may have a different composition than the bulk photoresist portion 205. The skin is typically formed by redepositing the dielectric residue from the low-k dielectric 203 and redepositing the polymer residue from the photoresist 205. In addition to the skin, a film 209 is further formed on the exposed sidewalls of the low-k dielectric 203. This film is typically formed from a polymer residue and is part of a low-k dielectric that has been damaged by ion bombardment in a dry etch process.

Referring again to FIG. 1, the photoresist strips the first portion (block 103). According to certain embodiments, this first portion includes a skin that is formed due to the etching process and that is often relatively difficult to remove. In this process, the wafer is exposed to a hydrogen-based plasma containing a weak oxidant and a fluorine-containing compound. For example, according to certain embodiments, exposing the wafer to a plasma of H 2 / CO 2 / NF 3 . As will be described later, a relatively small amount of fluorine-containing compound is used in this treatment. As an example, the flow rate of H 2 is about 20,000 sccm (20 slpm), the flow rate of CO 2 is 800 sccm (0.8 slpm), and the flow rate of NF 3 is 5 sccm. Each flow rate may vary from embodiment to embodiment. The flow rate of H 2 is 2 digits larger than the flow rate of CO 2 and 4 digits larger than the flow rate of NF 3 . According to certain embodiments, the CO 2 flow rate is at least one order of magnitude greater than the NF 3 flow rate. The above range may be appropriately applied to other weak oxidizing agents and fluorine-containing compounds.

  This process is typically performed in a reaction chamber that is separate from the chamber in which the etching was performed. Such a reaction chamber may be referred to as a stand-alone “stripping part”. Any device having an appropriate plasma reaction chamber may be used. In this system, either direct (in situ) plasma or remote plasma may be supplied.

  It should be noted that the process 103 may be utilized in certain embodiments instead of conventional oxygen-based stripping. Conventional oxygen-based stripping is typically performed in the same reaction chamber where the etching was performed, and exposure to an oxygen-based plasma is usually performed. Such partial stripping due to oxidation can damage some low-k dielectric materials and is not performed in certain embodiments. Thus, in certain embodiments, in process 101, a wafer that has not yet been subjected to such a stripping process in an etching chamber is provided.

  Referring again to FIG. 1, in the next process, the wafer is exposed to a hydrogen-based plasma containing a weak oxidant to strip the bulk photoresist and / or remove etch-related materials (block). 105). According to certain embodiments, this process does not utilize fluorine, unlike the previous process. According to certain embodiments, the bulk and residue of the photoresist is removed in this process. The process may include a plurality of processes.

  The total gas flow and relative amounts of weak oxidizers and fluorine-containing compounds, and other conditions in the stripping chamber, among other factors, include the type of plasma (downstream or direct), RF power, It may vary depending on the chamber pressure, the size of the substrate (wafer), and the type of weak oxidant utilized. According to some examples utilizing the Novellus Gamma ™ system (downstream plasma system), the plasma may contain between about 0.1% and 10% carbon dioxide by volume, It may contain between about 5 ppm and 10% by volume of nitrogen trifluoride (if included).

  In addition to hydrogen, a weak oxidant and a fluorine-containing gas, a carrier gas such as helium, argon or nitrogen may be used. The carrier gas is usually a non-reactive gas. For safety reasons at the time of shipment and handling, commercially available hydrogen can be used in a state mixed with a rare gas such as helium. Such a commercially available mixed gas may be used in the method according to the present invention.

  After most of the photoresist and etch residues are removed by plasma stripping in process 105, one or more plasma stripping or wet cleaning processes may be additionally performed. It should also be noted that in devices with multiple stations, processes 103 and 105 can each be performed across one or more stations.

  The wafer is typically temperature controlled while it is exposed to the plasma. Specifically, the temperature is about 200 degrees Celsius or less, about 160 degrees Celsius or less, about 150 degrees Celsius or less, about 140 degrees Celsius or less, about 130 degrees Celsius or less, about 120 degrees Celsius or less, about 110 degrees Celsius or less, It is controlled to be about 100 degrees Celsius or less, about 90 degrees Celsius or less, about 80 degrees Celsius or less, or about 60 degrees Celsius or less. According to certain embodiments, the temperature of the substrate is maintained below about 90 degrees Celsius. This relatively low temperature has been found to be important in certain embodiments to prevent significant damage to the ULK membrane.

  FIG. 3A shows the patterned ultra low-k dielectric layer 303, hard mask layer 315, and silicon carbide layer 301 after the photoresist has been removed as described above. The low-k dielectric layer 303 is etched with concave features 310 that are vias or trenches. Feature 310 has a side wall 317 and a bottom 319. It has been found that if the temperature during removal of the photoresist is too high, the low-k material near the sidewall 317 is damaged. One method for testing this damage is HF immersion. For example, it is immersed in a 100: 1 dilution of HF for 45 seconds. As an example, a photoresist removal process as described above is performed at 90 degrees Celsius and compared to a process that uses the same chemistry but is performed at 280 degrees Celsius. FIG. 3B shows the result at 317 ″ to show the profile of the feature when stripped at 280 degrees Celsius and the profile of the feature at 317 ′ when stripped at 90 degrees Celsius. Profile 317 ″ has been found to be substantially unchanged from the profile of the feature when stripped, but profile 317 ″ is curved inward. The area between these two profiles is the area damaged by the high temperature stripping process. Higher temperature processes may also remove a certain amount of etch stop material from the bottom of the feature.

  The higher the temperature, the higher the etching rate, but it has been found that increasing the temperature increases the amount of fluorine required for etching. As a result, damage to the dielectric increases. However, damage can occur even if the exposure time is prolonged due to the low temperature. However, it has been found that if the temperature is set to the above range, damage can be stopped or suppressed within the constraints of such competing effects.

For example, the following processing conditions were adopted in order to realize stripping with little damage.
Station 1: H 2 20 slpm / CO 2 0.8 slpm / NF 3 5 sccm
Station 2-5: H 2 20 slpm / CO 2 0.8 slpm
Station 1-5: 0.9 Torr / 90 degrees Celsius / RF plasma 3.5 kW / 103 seconds per station

  According to certain embodiments, for one or more treatments, the temperature is raised after exposure to the fluorine-containing plasma. For example, the temperature during exposure to the fluorine-based plasma may be a temperature less than 160 degrees Celsius or less than 90 degrees Celsius. The temperature is raised prior to or during exposure to one or more treatments utilizing a fluorine-free plasma. According to certain embodiments, the temperature may be raised in stages, with the later station becoming a higher temperature than the previous station. The temperature after the temperature rise may be within the above-described range, or may be higher than the above-described range. For example, according to certain embodiments, later stations may utilize high temperatures such as 285 degrees Celsius. However, according to many embodiments, it is kept cool throughout the stripping process.

In the above description, an example in which the photoresist is removed using hydrogen-based plasma at a low temperature has been described. In particular, a process has been described that maintains the wafer temperature at low temperatures when exposing photoresist and etch-related residues to a plasma generated from hydrogen gas. The low temperature is, for example, less than about 200 degrees Celsius, less than about 160 degrees Celsius, less than about 150 degrees Celsius, less than about 140 degrees Celsius, less than about 130 degrees Celsius, less than about 120 degrees Celsius, less than about 110 degrees Celsius, Less than 100 degrees Celsius, less than about 90 degrees Celsius, less than about 80 degrees Celsius, or less than about 60 degrees Celsius. According to certain embodiments, the gas used to generate the plasma consists essentially of hydrogen gas in one or more processes. According to another embodiment, one or more of the weak oxidant, fluorine-containing gas, and carrier gas may be added to the hydrogen gas in one or more processes, as described above. Examples of processing gas chemicals employed to generate plasma for low temperature exposure processing include H 2 , H 2 / CO 2 , H 2 / CO 2 / NF 3 and H 2 / NF 3. is there. Instead of CO 2 and NF 3 or in addition to CO 2 and BF 3 , other weak oxidants and fluorine-containing agents described above are included. Depending on the characteristics of the photoresist and etching residues, some or all of the removal processes described in FIGS. 2A-2C may be used.

For example, the gas used to generate the hydrogen-based plasma to remove “skins” may be substantially free of CO 2 or other weak oxidants. Also, according to certain embodiments, NF 3 or other fluorine-containing gas may be substantially free. The gas used to generate the hydrogen-based plasma for removing the bulk photoresist may be substantially free of CO 2 or other weak oxidants. In many embodiments, as described above, the NF 3 or other fluorine-containing gas may be substantially free. However, NF 3 or other fluorine-containing gas may be included in certain embodiments.

<Device>
As described above, any suitable plasma reaction chamber apparatus may be utilized. Suitable plasma chambers and systems include the Gamma 2100, 2130 I 2 CP (interlaced inductively coupled plasma) G400, and GxT from Novellus Systems, Inc. (San Jose, Calif.). Other systems include Axcelis Technologies Inc. (Fusion line), PSK Tech Inc. (Rockville, Maryland, USA). TERA21, Mattson Technology Inc. (Korea). There is Aspen manufactured by the company (Fremont, California, USA). Various stripping chambers may also be configured on the cluster tool. For example, the stripping chamber may be added to a Centura cluster tool manufactured by Applied Materials (Santa Clara, Calif., USA).

  FIG. 4A is a schematic diagram illustrating a side view of a downstream plasma apparatus 400 suitable for implementing the present invention on a wafer. In the apparatus 400, the plasma source 411 and the exposure chamber 401 are separated by a shower head assembly 417. In the exposure chamber 401, the wafer 403 is placed on a platen (or stage) 405. The platen 405 is provided with a heating / cooling element. According to some embodiments, the platen 405 is configured to apply a bias to the wafer 403. The inside of the exposure chamber 401 is set to a low pressure by a vacuum pump through the conduit 407. Gaseous hydrogen (with or without diluent / carrier gas), carbon dioxide (or other weak oxidant), and, if included, nitrogen trifluoride (or other fluorine-containing gas) ) Provides a gas flow through the inlet 409 and into the plasma source 411 of the apparatus. The plasma source 411 is partially surrounded by the induction coil 413. The induction coil 413 is connected to the power source 415. The operation will be described. When mixed gas is introduced into the plasma source 411 and energy is applied to the induction coil 413, plasma is generated in the plasma source 411. The showerhead assembly 417 stops the flow of some ions and directs the flow of neutral species into the exposure chamber 401 when a voltage is applied. As described above, the temperature of the wafer 403 may be controlled and / or an RF bias may be applied. The plasma source 411 and the induction coil 413 may utilize various configurations and structures. For example, the induction coil 413 may be wound around the plasma source 411 in an interlace pattern. According to another example, the plasma source 411 may have a dome shape instead of a cylindrical shape. The controller 450 may be connected to the components of the processing chamber and may control the composition, pressure, temperature, and indexing of the wafer in the stripping process. A machine readable medium containing instructions for controlling the processing conditions of the above processing may be coupled to the controller.

  As described above, according to some embodiments, the apparatus according to the present invention is a stripping section specialized for stripping photoresist from a wafer. In general, such a stripping tool includes a plurality of wafer processing stations and can process a plurality of wafers simultaneously. FIG. 4B is a simplified block diagram illustrating a top view of a multi-station wafer stripping tool 430 utilized in accordance with the present invention. The stripping tool 430 includes five stripping stations 433, 435, 437, 439 and 441, and one load station 431. The stripping tool 430 is configured so that one station can be processed per station and all stations are exposed to a common vacuum. Each of the stripping stations 433, 435, 437, 439 and 441 has its own RF power source. The load station 431 is typically mounted with a load lock station so that a plurality of wafers can be placed in the stripping tool 430 without interrupting the vacuum. The load station 431 may further comprise a heat lamp for preheating the wafer before being transported to the stripping station for photoresist stripping. The stripping station 441 is typically mounted with a load lock station so that a plurality of wafers can be removed from the stripping tool 430 without interrupting the vacuum. A robot arm 443 transports wafers between stations.

  In the normal manufacturing mode, wafers are processed in a batch mode. Batch processing improves wafer throughput and is often used in manufacturing processes. In the batch method, each wafer is transported to each of the stations 431, 433, 435, 437, 439 and 441 and processed at each station. For example, a normal batch process proceeds as follows. The wafer is first loaded into a load station 431 where the wafer is preheated with a heat lamp. Subsequently, the robot arm 443 transports the wafer to a stripping station 433 that performs plasma processing for a period sufficient to strip about one-fifth of the photoresist using fluorine-based plasma. Robot arm 443 then transports the wafer to a stripping station 435 that is plasma treated in a fluorine-free process for a period sufficient to strip another approximately one fifth from the remaining photoresist. Processing continues in this order, and the wafers are processed in stripping stations 437, 439 and 441. At the stripping station 441, most of the photoresist should be removed and the wafer is then removed from the stripping tool.

  Various details are omitted for the sake of clarity, but the configuration may be changed in various ways. Thus, the above-described examples are to be construed as illustrative and not limiting of the invention, and the invention is limited to the details set forth herein. Rather, it can be modified in the claims.

Claims (12)

  1. A method of removing material from a dielectric layer on a workpiece that is part of an integrated circuit being fabricated after an etching process, comprising:
    Forming a first plasma from a gas comprising hydrogen and a fluorine-containing compound;
    Exposing the workpiece to the first plasma;
    Forming a second plasma from a gas containing a hydrogen material;
    Exposing the workpiece to the second plasma,
    Wherein the temperature of the workpiece is maintained at a temperature below Celsius 160 degrees,
    The second plasma is substantially free of fluorine,
    The method of removing the photoresist from the low-k dielectric layer, wherein the first plasma and the second plasma do not contain oxygen molecules and have a dielectric constant of less than 4.0.
  2. The method of claim 1 wherein the temperature of the workpiece, which is maintained at a temperature below 100 degrees Celsius.
  3. The method of claim 1 wherein the temperature of the workpiece, which is maintained at a temperature below Celsius 90 degrees.
  4.   The method according to any one of claims 1 to 3, wherein the gas for forming the first plasma further comprises a weak oxidant.
  5.   The method of claim 4, wherein the weak oxidant comprises at least one of carbon dioxide, carbon monoxide, nitrous oxide, nitric oxide, nitrogen dioxide, and water.
  6.   The method of claim 4, wherein the weak oxidant is carbon dioxide.
  7. The fluorine-containing compound includes nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), hexafluoroethane (C 2 F 6 ), tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), difluoro Methane (CH 2 F 2 ), Octofluoropropane (C 3 F 8 ), Octofluorocyclobutane (C 4 F 8 ), Octofluoro [1-] butane (C 4 F 8 ), Octofluoro [2-] butane ( The method according to any one of claims 1 to 6, comprising at least one of C 4 4F 8 ), octofluoroisobutylene (C 4 F 8 ), and fluorine (F 2 ).
  8.   The method according to claim 7, wherein the fluorine-containing compound is nitrogen trifluoride.
  9. 9. The method according to any one of claims 1 to 8 , wherein the workpiece has not been subjected to a conventional oxygen-based plasma photoresist stripping process.
  10. 10. A method according to any one of claims 1 to 9 , wherein the material removed from the dielectric layer comprises a photoresist and / or residue resulting from the etching process.
  11. An apparatus for removing material from the surface of a workpiece,
    A reaction chamber;
    A controller that executes a series of instructions,
    The reaction chamber comprises
    A plasma source;
    A showerhead located downstream of the plasma source;
    A workpiece support located downstream of the showerhead,
    The workpiece support includes a temperature control mechanism and a pedestal for controlling the temperature of the workpiece supported on the workpiece support,
    The sequence of instructions is
    Instructions for forming a first plasma from a gas comprising hydrogen, a weak oxidant and a fluorine-containing compound;
    Instructions for exposing the workpiece to the first plasma;
    Instructions for forming a second plasma from a gas comprising hydrogen and a weak oxidant;
    Instructions for exposing the workpiece to the second plasma;
    The step of exposing said first plasma, and, in the step of exposing the second plasma, the temperature of the workpiece is maintained at a temperature below Celsius 160 degrees, the second plasma is substantially Does not contain fluorine,
    The first plasma and the second plasma remove photoresist from a low-k dielectric layer that does not contain oxygen molecules and has a dielectric constant of less than 4.0;
    apparatus.
  12. A method of manufacturing an integrated circuit, wherein after the etching process of the method according to any one of claims 1 to 10 , material is removed from a dielectric layer on a workpiece that is part of the integrated circuit being manufactured. A method of manufacturing an integrated circuit comprising the step of removing.
JP2012543254A 2009-12-11 2010-12-08 Method and apparatus for removing material from a dielectric layer on a workpiece and method for manufacturing an integrated circuit comprising removing material from a dielectric layer on a workpiece Active JP5911068B2 (en)

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PCT/US2010/059517 WO2011072042A2 (en) 2009-12-11 2010-12-08 Low damage photoresist strip method for low-k dielectrics

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