JP5843893B2 - 高い絶縁破壊電圧の埋め込まれたmimキャパシタ構造体 - Google Patents
高い絶縁破壊電圧の埋め込まれたmimキャパシタ構造体 Download PDFInfo
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- JP5843893B2 JP5843893B2 JP2014007523A JP2014007523A JP5843893B2 JP 5843893 B2 JP5843893 B2 JP 5843893B2 JP 2014007523 A JP2014007523 A JP 2014007523A JP 2014007523 A JP2014007523 A JP 2014007523A JP 5843893 B2 JP5843893 B2 JP 5843893B2
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- capacitors
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- 239000003990 capacitor Substances 0.000 title claims description 174
- 230000015556 catabolic process Effects 0.000 title description 35
- 239000000463 material Substances 0.000 claims description 91
- 238000000034 method Methods 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 65
- 229910052751 metal Inorganic materials 0.000 claims description 65
- 239000004065 semiconductor Substances 0.000 claims description 28
- 229910005883 NiSi Inorganic materials 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 136
- 230000008569 process Effects 0.000 description 43
- 238000004519 manufacturing process Methods 0.000 description 26
- 238000009792 diffusion process Methods 0.000 description 17
- 238000005530 etching Methods 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- 238000013461 design Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000006249 magnetic particle Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021471 metal-silicon alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
101 半導体基板
103 拡散領域
105 NiSi接点
107a 接触部
107b 接触部
109 下部電極
111 誘電体
113 上部電極
115a 上部プレート金属
115b 上部プレート金属
200 MIMキャパシタ
201 基板
203 第1絶縁層
204 ゲート材料
205 ドーピング
207 第1金属層
209 第2絶縁層
209a 第1ホール部分
209b 第2ホール部分
211 第3絶縁層
213 接触部
213a 第3ホール部分
215 第4絶縁層
215a 第4ホール部分
217 下部電極
219 誘電体
221 上部電極
221a 第5ホール部分
222 第5絶縁層
223 接触部
225 ストレージ金属プレート
227 共通プレート
C1 キャパシタ
C2 キャパシタ
C3 キャパシタ
C4 キャパシタ
Claims (14)
- ゲート材料上に絶縁層を形成し、
複数の金属接触部を形成し、
第1及び第2キャパシタを形成することであって、前記キャパシタの各々が、第1金属層から形成される下部電極を形成し、前記下部電極の表面を覆うように誘電体を形成し、及び前記誘電体に形成される第2金属層から上部電極を形成する、第1及び第2キャパシタを形成し、
前記金属接触部を介して前記第1及び第2キャパシタの下部電極の各々を第1のゲート材料に接続することであって、前記第1及び第2キャパシタが前記第1のゲート材料を介して直列に接続され、
第3及び第4キャパシタを形成することであって、各々のキャパシタが、下部電極を形成し、前記下部電極の表面を覆うように誘電体を形成し、及び前記誘電体に形成される上部電極を形成し、前記第3及び第4キャパシタが、第2のゲート材料を介して直列に接続され、
前記金属接触部を介して前記第3及び第4キャパシタの下部電極の各々を第2のゲート材料に接続することであって、前記第3及び第4キャパシタが前記第2のゲート材料を介して直列に接続されること、
を含み、
前記第2及び第4キャパシタの上部電極が、共通金属部を共有し、前記共通金属部が、第1の金属プレートを介して第1電圧端子に電気的に接続され、
前記第1及び第3キャパシタの上部電極が、第2の金属プレートを介して第2電圧端子に電気的に接続され、
前記第1、第2、第3及び第4キャパシタの下部電極、誘電体及び上部電極が、井戸型の構造体である、半導体装置の組立方法。 - 前記ゲート材料が、第1層及び第2層を含む、請求項1に記載の方法。
- 前記ゲート材料の第1層がNiSi材料である、請求項2に記載の方法。
- 前記ゲート材料の第2層が、n+ドーピングされた材料である、請求項2に記載の方法。
- 前記ゲート材料の第2層が、p+ドーピングされた材料である、請求項2に記載の方法。
- 前記複数のキャパシタが、金属−絶縁体−金属(MIM)キャパシタタイプである、請求項1に記載の方法。
- 前記誘電体が、高誘電率誘電体タイプである、請求項1に記載の方法。
- ゲート材料上に絶縁層を形成する段階と、
複数の金属接触部を形成する段階と、
第1及び第2キャパシタを形成する段階であって、前記キャパシタの各々が、第1金属層から形成される下部電極を形成し、前記下部電極の表面を覆うように誘電体を形成し、及び前記誘電体に形成される第2金属層から上部電極を形成する、第1及び第2キャパシタを形成する段階と、
前記金属接触部を介して前記第1及び第2キャパシタの下部電極の各々を第1のゲート材料に接続する段階であって、前記第1及び第2キャパシタが前記第1のゲート材料を介して直列に接続される段階と、
第3及び第4キャパシタを形成する段階であって、各々のキャパシタが、下部電極を形成し、前記下部電極の表面を覆うように誘電体を形成し、及び前記誘電体に形成される上部電極を形成し、前記第3及び第4キャパシタが、第2のゲート材料を介して直列に接続される段階と、
前記金属接触部を介して前記第3及び第4キャパシタの下部電極の各々を第2のゲート材料に接続する段階であって、前記第3及び第4キャパシタが前記第2のゲート材料を介して直列に接続される段階と、
を含み、
前記第2キャパシタ及び第4キャパシタの上部電極が、共通金属部を共有し、前記共通金属部が、第1の金属プレートを介して第1電圧端子に電気的に接続され、
前記第1キャパシタ及び第3キャパシタの上部電極が、第2の金属プレートを介して第2電圧端子に電気的に接続され、
前記第1、第2、第3及び第4キャパシタの下部電極、誘電体及び上部電極が、井戸型の構造体である、半導体装置の組立方法。 - 前記ゲート材料が、第1層及び第2層を含む、請求項8に記載の方法。
- 前記ゲート材料の第1層がNiSi材料である、請求項9に記載の方法。
- 前記ゲート材料の第2層が、n+ドーピングされた材料である、請求項9に記載の方法。
- 前記ゲート材料の第2層が、p+ドーピングされた材料である、請求項9に記載の方法。
- 前記複数のキャパシタが、金属−絶縁体−金属(MIM)キャパシタタイプである、請求項8に記載の方法。
- 前記誘電体が高誘電率誘電体タイプである、請求項8に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/536,819 US8604586B2 (en) | 2009-08-06 | 2009-08-06 | High breakdown voltage embedded MIM capacitor structure |
US12/536,819 | 2009-08-06 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012523978A Division JP5538539B2 (ja) | 2009-08-06 | 2010-08-06 | 高い絶縁破壊電圧の埋め込まれたmimキャパシタ構造体 |
Publications (2)
Publication Number | Publication Date |
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JP2014075613A JP2014075613A (ja) | 2014-04-24 |
JP5843893B2 true JP5843893B2 (ja) | 2016-01-13 |
Family
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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JP2012523978A Expired - Fee Related JP5538539B2 (ja) | 2009-08-06 | 2010-08-06 | 高い絶縁破壊電圧の埋め込まれたmimキャパシタ構造体 |
JP2014007523A Expired - Fee Related JP5843893B2 (ja) | 2009-08-06 | 2014-01-20 | 高い絶縁破壊電圧の埋め込まれたmimキャパシタ構造体 |
Family Applications Before (1)
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JP2012523978A Expired - Fee Related JP5538539B2 (ja) | 2009-08-06 | 2010-08-06 | 高い絶縁破壊電圧の埋め込まれたmimキャパシタ構造体 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8604586B2 (ja) |
EP (1) | EP2462610A1 (ja) |
JP (2) | JP5538539B2 (ja) |
KR (1) | KR101315911B1 (ja) |
CN (1) | CN102473596B (ja) |
TW (1) | TW201117355A (ja) |
WO (1) | WO2011017623A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US8604586B2 (en) | 2009-08-06 | 2013-12-10 | Qualcomm Incorporated | High breakdown voltage embedded MIM capacitor structure |
CN103138725A (zh) * | 2013-01-11 | 2013-06-05 | 华为技术有限公司 | 具有金属板电容的电路及射频开关、低噪声放大器 |
US9105602B2 (en) | 2013-12-23 | 2015-08-11 | Qualcomm Incorporated | Embedded three-dimensional capacitor |
US9502586B1 (en) * | 2015-09-14 | 2016-11-22 | Qualcomm Incorporated | Backside coupled symmetric varactor structure |
US9601545B1 (en) * | 2015-10-15 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Series MIM structures compatible with RRAM process |
AU2016359149B2 (en) * | 2015-11-25 | 2018-08-23 | Google Llc | Prism-based eye tracking |
TWI709248B (zh) | 2015-12-10 | 2020-11-01 | 聯華電子股份有限公司 | 電容及其製作方法 |
US10026731B1 (en) * | 2017-04-14 | 2018-07-17 | Qualcomm Incorporated | Compound semiconductor transistor integration with high density capacitor |
CN107799519A (zh) * | 2017-11-20 | 2018-03-13 | 荣湃半导体(上海)有限公司 | 一种高压隔离电路 |
JP7179634B2 (ja) * | 2019-02-07 | 2022-11-29 | 株式会社東芝 | コンデンサ及びコンデンサモジュール |
US20210013318A1 (en) * | 2019-07-11 | 2021-01-14 | Micron Technology, Inc. | Electrode formation |
US20230197597A1 (en) * | 2021-12-17 | 2023-06-22 | Wolfspeed, Inc. | Configurable metal - insulator - metal capacitor and devices and processes implementing the same |
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KR100231404B1 (ko) * | 1996-02-22 | 1999-11-15 | 가네꼬 히사시 | 다수의 값을 갖는 소형 반도체 메모리 디바이스 |
JP2768341B2 (ja) * | 1996-02-22 | 1998-06-25 | 日本電気株式会社 | 半導体記憶装置 |
JP2940485B2 (ja) * | 1996-09-13 | 1999-08-25 | 日本電気株式会社 | 半導体記憶装置 |
JPH1012838A (ja) * | 1996-06-21 | 1998-01-16 | Mitsubishi Electric Corp | 半導体装置 |
JP3085280B2 (ja) | 1998-05-15 | 2000-09-04 | 日本電気株式会社 | 多値dram半導体装置 |
JP2000150813A (ja) * | 1998-09-02 | 2000-05-30 | Sanyo Electric Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP2001196559A (ja) * | 2000-01-13 | 2001-07-19 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2001196560A (ja) * | 2000-01-14 | 2001-07-19 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US7105891B2 (en) * | 2002-07-15 | 2006-09-12 | Texas Instruments Incorporated | Gate structure and method |
US6919233B2 (en) | 2002-12-31 | 2005-07-19 | Texas Instruments Incorporated | MIM capacitors and methods for fabricating same |
KR100655074B1 (ko) * | 2004-11-11 | 2006-12-11 | 삼성전자주식회사 | 스토리지 커패시터 및 그의 제조방법 |
KR100701697B1 (ko) * | 2005-06-29 | 2007-03-29 | 주식회사 하이닉스반도체 | 듀얼 폴리사이드 게이트를 갖는 씨모스 소자의 제조방법 |
KR100675287B1 (ko) * | 2005-11-03 | 2007-01-29 | 삼성전자주식회사 | 커플링 커패시터 및 이를 이용하는 메모리 소자 |
JP2008108897A (ja) * | 2006-10-25 | 2008-05-08 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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US8604586B2 (en) | 2009-08-06 | 2013-12-10 | Qualcomm Incorporated | High breakdown voltage embedded MIM capacitor structure |
-
2009
- 2009-08-06 US US12/536,819 patent/US8604586B2/en not_active Expired - Fee Related
-
2010
- 2010-08-06 CN CN201080034956.3A patent/CN102473596B/zh active Active
- 2010-08-06 WO PCT/US2010/044724 patent/WO2011017623A1/en active Application Filing
- 2010-08-06 EP EP10744636A patent/EP2462610A1/en not_active Withdrawn
- 2010-08-06 KR KR1020127005953A patent/KR101315911B1/ko not_active IP Right Cessation
- 2010-08-06 JP JP2012523978A patent/JP5538539B2/ja not_active Expired - Fee Related
- 2010-08-06 TW TW099126353A patent/TW201117355A/zh unknown
-
2013
- 2013-11-11 US US14/076,395 patent/US8889522B2/en not_active Expired - Fee Related
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2014
- 2014-01-20 JP JP2014007523A patent/JP5843893B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2013501385A (ja) | 2013-01-10 |
EP2462610A1 (en) | 2012-06-13 |
KR20120034129A (ko) | 2012-04-09 |
KR101315911B1 (ko) | 2013-10-10 |
JP2014075613A (ja) | 2014-04-24 |
US8889522B2 (en) | 2014-11-18 |
CN102473596B (zh) | 2014-11-19 |
US20140065792A1 (en) | 2014-03-06 |
TW201117355A (en) | 2011-05-16 |
JP5538539B2 (ja) | 2014-07-02 |
US20110031586A1 (en) | 2011-02-10 |
CN102473596A (zh) | 2012-05-23 |
US8604586B2 (en) | 2013-12-10 |
WO2011017623A1 (en) | 2011-02-10 |
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